Scaleflux, Inc.

Lsi Corporation

Seagate Technology Incorporated

Agere Systems Inc.

Sandisk Technologies Inc.

Avago Technologies General IP (Singapore) Pte. Ltd.

Hao Zhong

Fei Sun

Yang Liu

Shaohua Yang

Tong Zhang

Weijun Tan

Yuan Xing Lee

Earl T Cohen

Zongwang Li

Yang Han

Richard Rauschmayer

Changyou Xu

Yan Li

Kelly K Fitzpatrick

George Mathew

Radoslav Danilak

Kiran Kumar Gunnam

Robert Barry Wood

Nils Graef

Jea Hyun

Hairong Sun

Alexander Hubris

Zhengang Chen

Hongwei Song

John Strasser

German S Feyh

Ned Plasson

Harley Burger

Mark Brinicombe

Ching-Fu Wu

Yangyang Pan

Lee Xing Yuan

A method according to embodiments includes: storing an entire hash table of a table R in memory of a computational storage device; storing a second table S in storage media of the computational storage device, the table R being smaller than the table S, wherein the hash JOIN operation is directed to combining a c-th column in the table S and a c-th column in the table R; wherein, for each row of the table S, the computational storage device configured to perform a method, including: applying a hash function to a value of the c-th column to provide a hash result; looking up the hash result in the hash table stored in the memory of the computational storage device; and if the hash result is found, sending the row of the table S and a corresponding row index of the table R to the host computing system.

Using in-storage computation to improve the performance of hash join for database and data analytics

A method for host-side data classification according to embodiments, includes: writing a data sector directly from a host to a storage device; storing the data sector in the storage device; sending a write completion acknowledgement from the storage device to the host; in the background: classifying the data sector on the host to estimate an expected lifetime of the data sector; assigning a data type index to the data sector based on the expected lifetime of the data sector; and asynchronously sending the data type index for the data sector from the host to the storage device.

Solid-state storage device speed performance and endurance through host-side data classification and embedded write caching

A host-assisted data deduplication system, including: a storage device including a controller, memory, and a write cache; and a host including a data duplication module coupled to the storage device, wherein the controller of the storage device is configured to write a data sector received from the host into the write cache in the storage device and to send a write completion to the host immediately after writing the data sector to the write cache; wherein the data duplication module is configured to detect whether the data sector is identical to another data sector stored in the memory of the storage device and to asynchronously send a duplicate detection result to the controller of the storage device, and wherein the controller of the storage device is configured to perform a data deduplication process for the data sector stored in the write cache based on the duplicate detection result.

Realizing host-assisted device-level data deduplication on solid-state data storage devices with embedded non-volatile memory

An infrastructure and method for storing compressed data. On a host, a data zero forcing system causes an unused portion at a tail end of a data sector to be forced to all zeros before being written. On a storage device comprising solid state memory, a zero tail detection system detects and removes a tail end of zeros in the data sector to create a variable size data chunk, and allocates a segment for storing the variable size data chunk. A variable size mapping system is provided that includes: a mapping table that maps a logical block address (LBA) of the variable size data chunk to a physical block address (PBA) entry, wherein the PBA entry includes a segment ID and an index; and a segment utilization table which, for each of a plurality of segments, provides a size of each variable size data chunk stored in the segment.

Data storage efficiency using storage devices with variable-size internal data mapping

Methods, systems and computer-readable storage media for determining a new optimal read threshold voltage associated with a group of pages of non-volatile memory. It is determined whether the current optimal read threshold voltage associated with the group of pages is out of tolerance based at least in part on a retention drift history associated with the group of pages. Upon determining that the current optimal read threshold voltage is out of tolerance, reference cells associated with the group of pages are written with a pattern having a known statistical distribution of ones and zeroes. The new optimal read threshold voltage associated with the group of pages is determined by reading the reference cells, and the retention drift history associated with the group of pages is updated with the new optimal read threshold voltage and an indication of a new reference cell generation.

Retention-drift-history-based non-volatile memory read threshold optimization

An enhanced FTL system and method are provided for eliminating redundant write operations. A method is disclosed, including: processing a data write operation from a host that deploys a journaling scheme, wherein the data write operation includes a specified LBA that maps to a PBA in a SSD memory; calculating a signature of a data block during a write operation; detecting whether the data write should be handled as journal or non-journal write operation without assistance from the host; in response to a detected journal write operation, allocating a new PBA, writing the data block to the new PBA, updating a mapping table with a new LBA-PBA mapping, and inserting the signature into a signature table for the new LBA-PBA mapping; and in response to a detected non-journal write operation, mapping the specified LBA to an existing PBA if the signature matches a stored signature in the mapping table.

Enhancing flash translation layer to improve performance of databases and filesystems

A system, method and program product for exploiting in-storage transparent compression. A storage infrastructure is disclosed that includes: a storage device having physical block address (PBA) storage of a defined capacity, a transparent compression system that compresses data written to the PBA storage, and a logical block address-to-physical block address mapping table; and a host having a memory management system that includes: an initialization system that allocates an amount of logical block address (LBA) storage for the host having a capacity greater than the defined capacity of the PBA storage, and that creates a dummy file that consumes LBA storage without consuming any PBA storage; a system that gathers current PBA and LBA usage information. The dummy file manager may adjust the size of the dummy file by truncating or appending sectors to the dummy file using a filesystem on the host, or using an allocation or deallocation function that does not incur any input/output (I/O) operations within the storage device. Dummy storage file sectors of the LBA storage may be mapped to dummy PBA storage that does not consume any physical storage in response to detecting a predefined content pattern indicative of dummy file sectors. The memory management system may device the LBA storage into partitions, with each partition receiving a dummy file.

Storage infrastructure and method for exploiting in-storage transparent compression using a dummy file that consumes LBA storage without consuming PBA storage

A storage aware memory controller for managing a physical storage system. A described controller: a system for mapping physical memory space into a memory region and a storage region; a system for applying different error protections schemes, in which a fine-grained memory fault tolerance scheme is applied to data in the memory region and a course-grained memory fault tolerance scheme is applied to data in the storage region; and a storage file system that includes a mapping table for mapping logical addresses to physical addresses for data stored in the storage region.

In-memory data storage with adaptive memory fault tolerance

A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array. A given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array. The given accelerated soft read operation may comprise a sequence of multiple hard read operations including a hard read operation directed to the non-upper page and one or more hard read operations directed to the corresponding upper page.

Accelerated soft read for multi-level cell nonvolatile memories

Methods, systems and computer-readable storage media for selecting a retention drift predictor scheme, reading retention drift history associated with reference cells of a plurality of groups of pages of a non-volatile memory (NVM), and predicting values for an optimal read threshold voltage of at least some of the plurality of groups of pages. The predicting of values for an optimal read threshold voltage may be based at least on the selected retention drift predictor scheme and the read retention drift history.

A data storage system having a hashing engine for facilitating data deduplication. A device is provided that includes: a storage media; and a controller, wherein the controller includes a hashing engine for implementing a data deduplication process on data stored in the storage medium, wherein the hashing engine: inputs parameters from a host that specifies a sliding widow size and a boundary condition; implements a rolling hash function; and outputs a data chunk boundary.

Assisting data deduplication through in-memory computation

A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.

LDPC Erasure Decoding for Flash Memories

A system, method and program product that utilizes a hybrid fault tolerance system for managing data. A system includes: a system for partitioning memory into a set of partitions that includes a designated partition for storing immutable objects; a write system for storing an immutable object in the designated partition, wherein the immutable object is coded with a hardware-based fault tolerance system to generate a set of hardware-based codewords, and wherein the immutable object is further coded with a software-based fault tolerance system to generate a set of software-based codewords; a read system for retrieving the immutable object, wherein the read system decodes each hardware-based codeword for immutable object, and in response to a failed decoding of a hardware-based codeword, the read system decodes the software-based codeword containing a failed hardware-based codeword.

Protecting in-memory immutable objects through hybrid hardware/software-based memory fault tolerance

Storage infrastructures and methods that generate hash values based on error correction codes. A system is provided that includes: a code retrieval system implemented on a host having logic for issuing a redundancy read command to a storage system to retrieve a redundancy code for an identified data block; and a hashing system implemented on the host for hashing the redundancy code to generate a hash value based on the redundancy code. A storage system is also provided that includes: a memory for storing data blocks and associated redundancy codes; and a controller having: an input/output for receiving a hash value read command for a specified data block from a host and returning a hash value; a decoding system that extracts a redundancy code associated with the specified data block; and an in-memory hashing system for computing a hash operation on the redundancy code.

Error correction coding redundancy based data hashing

A storage aware memory controller and method for managing a physical storage system. A described controller includes: a system for mapping physical memory space into a memory region and a storage region; a system for applying different error protections schemes, in which a fine-grained memory fault tolerance scheme is applied to data in the memory region and a course-grained memory fault tolerance scheme is applied to data in the storage region; and an in-memory storage filesystem that compresses and stores individual pages of data in the storage region, wherein each page of data is compressed into a set of codewords that are codeword aligned such that no codeword shares compressed data from different pages, and wherein the in-memory storage filesystem stores a compression-aware logical block address (CA-LBA) for each page of data.

Growing community of inventors

Milpitas, CA, United States of America

Hao Zhong