Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Hao-Yu Tung

Igor Elkanovich

Hung-Yi Chang

Sheng-Fan Yang

Yu-Cheng Sun

Wei-Chiao Wang

Ming-Hsuan Wang

Wei-Chieh Liao

Yi-Tzeng Lin

An interposer routing structure includes a first trace layer, a bump layer, a second trace layer and a third trace layer. The first trace layer is configured to receive a power. The bump layer is coupled to a die. The second trace layer and the third trace layer are coupled between the first trace layer and the bump layer, and include multiple ground traces and multiple power traces. The ground traces are located on both sides of at least one of the power traces, so that the ground traces isolate the at least one power trace and multiple signal traces. The power traces of the second trace layer are coupled to each other by a connecting power trace, and the ground traces of the third trace layer are coupled to each other by a connecting ground trace.

Interposer routing structure and semiconductor package

A routing structure between dies is provided, including a trace layer, disposed on a substrate, wherein a plurality of routing paths is embedded in the trace layer. In addition, a first die and a second die are disposed on the trace layer and connected by the routing paths. A spacing gap between the first die and the second die is along a first direction and interfacing edges of the first die and the second die are extending along a second direction perpendicular to the first direction. Each of the routing paths includes a first straight portion in parallel to connect to the interfacing edges. The first straight portion has a slant angle with respect to the first direction other than 0&#xb0; and 90&#xb0;.

Routing structure between dies and method for arranging routing between dies

Growing community of inventors

Hsinchu, Taiwan

Hao-Yu Tung