Xilinx, Inc.

Hao Yu

Raymond Kong

Jun Liu

Brian S Martin

David P Schultz

Ashish Sirasao

Kevin Beazley

Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).

Dynamic port handling for isolated modules and dynamic function exchange

Time-multiplexing implementation of hardware accelerated functions includes associating each function of a plurality of functions from program code with an accelerator binary image specifying a hardware accelerated version of the associated function and determining which accelerator binary images are data independent. Using the computer hardware, the accelerator binary images can be scheduled for implementation in a programmable integrated circuit within each of a plurality of partial reconfiguration regions based on data independence.

Time-multiplexed implementation of hardware accelerated functions in a programmable integrated circuit

Method, apparatus and computer-readable medium for providing a partial reconfiguration of a reconfigurable module are described. In one example, a method reads a netlist for a design of a circuit comprising a reconfigurable module and sets the reconfigurable module to a first region. The method then generates a second region that encompasses the first region and places the design with the first region. The method routes the design with the second region and generates a partial bitstream for the reconfigurable module.

Extend routing range for partial reconfiguration

A device includes a platform implemented in programmable circuitry of the device. The platform is configured to communicate with a host data processing system. The device includes a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region is reserved for implementing user-specified circuitry. The device includes timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region.

Timing insulation circuitry for partial reconfiguration of programmable integrated circuits

Providing dynamic platform support for a programmable integrated circuit (IC) can include loading a circuit design for a programmable IC, wherein the circuit design specifies a link region coupled to a first infrastructure region by first connections, and a kernel region coupled to the first infrastructure region by second connections and generating a base platform from the circuit design by removing the first infrastructure region, the kernel region, and the second connections from the circuit design and adding a wrapper that includes the first connections. A new platform can be generated from the base platform where the new platform includes the link region and, within the wrapper, a second infrastructure region coupled to the link region by the first connections.

Dynamic platform support in programmable integrated circuits

Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.

Hierarchical partial reconfiguration for programmable integrated circuits

A method of implementing a partial reconfiguration in an integrated circuit device is described. The method comprises reading a netlist for a design of a circuit comprising a reconfigurable module; defining a first region of the integrated circuit device having the reconfigurable module; defining a second region that encompasses the first region; placing the reconfigurable module of the design in the first region, wherein the reconfigurable module comprises a partition pin of a plurality of available partition pins; selectively removing the partition pin; routing drivers and loads that are in the second region; and generating a partial bitstream for the reconfigurable module.

Method of enabling a partial reconfiguration in an integrated circuit device

Implementing a circuit design for partial reconfiguration can include routing, using a processor, a net of the circuit design that connects an endpoint within a reconfigurable module with an endpoint within static circuitry external to the reconfigurable module and forming, using the processor, a set of candidate nodes including nodes used to route the net. A node from the set of candidate nodes is determined as the partition pin for partial reconfiguration.

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Broomfield, CO, United States of America

Hao Yu