Taiwan Semiconductor Manufacturing Comp. Ltd.

Hao-Yi Tsai

Chen-Hua Douglas Yu

Tin-Hao Kuo

Chung-Shi Liu

Hung-Yi Kuo

Hsien-Wei Chen

Tsung-Yuan Yu

Chih-Hua Chen

Yu-Chih Huang

Yu-Chia Lai

Chih-Hsuan Tai

Mirng-Ji Lii

Shin-Puu Jeng

Ming Hung Tseng

Cheng-Chieh Hsieh

Tzu-Sung Huang

Yu-Feng Chen

Chi-Hui Lai

Kuo Lung Pan

Po-Yuan Teng

Tsung-Hsien Chiang

Ying-Ju Chen

Yen-Liang Lin

Shih-Wei Chen

Chih-Wei Lin

Chia-Hung Liu

Chao-Wen Shih

Yu-Wen Liu

Shih-Wei Liang

Shang-Yun Hou

Hsiu-Jen Lin

Chuei-Tang Wang

Tzuan-Horng Liu

Hsin-Yu Pan

Kuo-Chung Yee

Kai-Chiang Wu

Hsien-Ming Tu

Chih-Hao Chang

Tung-Liang Shao

Jie Chen

Shih-Hsun Hsu

Chang-Pin Huang

Ching-Hua Hsieh

Wei-Ting Chen

Ching-Jung Yang

Ming-Da Cheng

Hui-Jung Tsai

Chia-Lun Tsai

Ching-Feng Yang

Pei-Hsuan Lee

Chewn-Pu Jou

Yu-Hsiang Hu

Ming-Che Ho

Sen-Kuei Hsu

Chieh-Yen Chen

Vincent Chen

Chien Ling Hwang

Yen-Ping Wang

Chien-Hsiun Lee

Chien-Ling Hwang

Chia-Chun Miao

Hung-Jui Kuo

Han-Ping Pu

Pei-Haw Tsao

Chun-Cheng Lin

Ming-Kai Liu

Chi-Ming Tsai

Tzu-Chun Tang

Chih-Horng Chang

Hsueh-Chung Chen

Chun-Lin Lu

Chenming Hu

Jui-Pin Hung

Meng-Tse Chen

Chih-Hang Tung

Feng-Wei Kuo

Hui-Min Huang

Hsin-Hui Lee

Jyh-Cherng Sheu

Chun-Jen Chen

Min-Hsiang Hsu

Hao-Jan Pei

Hsin-Hung Liao

Chao-Yuan Su

Carlos H Diaz

Kong-Beng Thei

Wei-Hung Lin

Chien-Hsun Lee

Wen-Hsiung Lu

Tsung-Ding Wang

Ta-Pen Guo

Kuo-Ji Chen

Wei-Chih Chen

Harry Hak-Lay Chuang

Yi-Ming Sheu

Po-Han Wang

Jian-Hong Lin

Sheng-Chen Chung

Shih-Ming Chen

Ming-Yen Chiu

A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

Conductive traces in semiconductor devices and methods of forming same

A semiconductor package includes a first tier and a second tier underlying the first tier and including TIVs and third dies. The first tier includes a first redistribution structure and first and second dies disposed side-by-side and separated by a first insulating encapsulation. A surface of the first insulating encapsulation, surfaces of first die connectors of the first die, and truncated spherical surfaces of second die connectors of the second die are level. The first redistribution structure underlies the surfaces of the first insulating encapsulation and the first die connectors and the truncated spherical surfaces of the second die connectors. The third dies disposed below the first redistribution structure are electrically coupled to the first die through the first redistribution structure and laterally covered by a second insulating encapsulation. The TIVs penetrate through the second insulating encapsulation and are electrically coupled to the second die through the first redistribution structure.

Semiconductor package and manufacturing method thereof

A photonic integrated circuit has a central region and a peripheral region surrounding the central region. The photonic integrated circuit includes a semiconductor layer, a seal ring structure, and a plurality of silicon waveguides. The seal ring structure is disposed on the semiconductor layer. The seal ring structure is located in the peripheral region and has at least one recess recessing towards the central region from a top view. The seal ring structure is a continuous structure from the top view. The silicon waveguides are embedded in the semiconductor layer.

Photonic integrated circuit and package structure

A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.

Staggered metal mesh on backside of device die and method forming same

A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Package structure

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a first die disposed on and electrically coupled to a first redistribution structure and laterally covered by a first insulating encapsulation, a second die disposed over the first die and laterally covered by a second insulating encapsulation, a second redistribution structure interposed between and electrically coupled to the first and second dies, a third redistribution structure disposed on the second die and opposite to the second redistribution structure, and at least one thermal-dissipating feature embedded in a dielectric layer of the third redistribution structure and electrically isolated from a patterned conductive layer of the third redistribution structure through the dielectric layer. Through substrate vias of the first die are physically connected to the second redistribution structure or the first redistribution structure. The thermal-dissipating feature is thermally coupled to a back surface of the second die.

In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.

Integrated circuit package and method

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Polymer layers embedded with metal pads for heat dissipation

A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

Dielectric slots underneath conductive vias in interconnect structure of semiconductor package and method of forming the same

An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

Fingerprint sensor device and method

A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.

Integrated fan-out packages and methods of forming the same

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern. The conductive vias extend through the molded semiconductor device and are electrically connected with the redistribution pattern.

A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion.

Method of fabricating semiconductor structure

A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.

Semiconductor device and manufacturing method thereof

Growing community of inventors

Hsinchu, Taiwan

Hao-Yi Tsai