Xiamen Tianma Micro-electronics Co., Ltd.

Tianma Micro-electronics Co., Ltd.

Hao Wu

Poping Shen

Yiqiang Lin

Guozhao Chen

Yumin Xu

Yihua Zhu

Ying Sun

Min Huang

Shoujin Cai

Qiong Song

Huimin Xie

Wei Wu

Zhuo Deng

Renliang Zhu

Qian Yang

Wenqiang Yang

Liangliang Bei

Jun Xia

Provided are an array substrate, a display panel, and a display device. The array substrate includes a substrate, and touch electrodes and touch leads located at a side of the substrate. The touch lead extends along a first direction. The touch electrode includes a groove and a first portion that are arranged along the first direction. The touch electrodes include a first touch electrode. The touch leads include a first touch lead including a first line segment and a second line segment. A line width of the first line segment is smaller than a line width of the second line segment. Along a direction perpendicular to a plane of the substrate, the first touch lead overlaps the first touch electrode, the first line segment at least partially overlaps the first portion, and the second line segment at least partially overlaps the groove.

Array substrate, display panel, and display device

A display panel and a display device are provided. The display panel includes a plurality of data lines and a plurality of scan lines. An extending direction of the plurality of data lines intersects an extending direction of the plurality of scan lines. The plurality of scan lines includes at least one first scan line. The first scan line includes a first portion. Metal conductivity of the first portion is greater than or equal to metal conductivity of the plurality of data lines.

Display panel and display device

Display panel and display device are provided. Display panel has display area and bezel area and includes first and second panel edges connected and adjacent to each other and extending linearly in different directions, first functional circuit located in the bezel area and including first functional circuit units. First functional circuit units include first, second, and third circuit units. First circuit units are located at side of first panel edge and arranged linearly along first panel edge, second circuit units are located at side of second panel edge and arranged linearly along second panel edge, third circuit unit is located between first and second circuit units and close to position where first panel edge is connected to second panel edge. One third circuit unit is arranged in direction inclined to a direction in which one first circuit unit is arranged and direction in which one second circuit unit is arranged.

In the display panel, a display region includes a plurality of sub-pixels arranged in an array, and a non-display region includes a plurality of demultiplexers, a plurality of signal source lines and M timing control lines. Each of the plurality of demultiplexers includes N gating switches, where in the same demultiplexer, input terminals of a plurality of gating switches are electrically connected to the same signal source line, an output terminal of each of the plurality of gating switches is electrically connected to one column of sub-pixels, and control terminals of the plurality of gating switches are electrically connected to different timing control lines. data signals transmitted by at least two signal source lines electrically connected to at least two gating switches controlled by a timing control line have opposite voltage polarities.

A shift register includes n shift register units which are cascaded. Each shift register unit includes a shift module and multiple enable modules. The shift module of an i-th-level shift register unit is configured to receive and latch a shift signal output by the shift module in an (i&#x2212;1)-th-level shift register unit. The multiple enable modules of the i-th-level shift register unit are electrically connected to the shift module of the i-th-level shift register unit, and each of the multiple enable modules is configured to generate a gate driving signal according to the shift signal. n and i are positive integers, 1&#x2264;i&#x2264;n.

A display panel includes data lines and scanning lines in a display region, and a demultiplexer in a non-display region. The demultiplexer includes m branches. m is an integer. m&#x2265;2. Each branch includes a switching transistor which includes a first electrode coupled with an input terminal of the demultiplexer, a second electrode coupled with one of the data lines, and a control electrode for receiving a switching control signal. The demultiplexer includes a first demultiplexer including a compensation transistor, of which first and second electrodes are short-circuited. The compensation transistor is coupled with the data line and has a control electrode for receiving a compensation control signal. The compensation control signal received by the compensation transistor in the branch has one functional rising edge in a period during which the scanning line provides an effective level signal once.

Disclosed is an array substrate. The array substrate includes a substrate and a pixel unit array. A first side of each row of pixel units is provided with a first scanning line corresponding to the row of pixel units, and the first scanning line is connected to switch elements of first-type pixel units in the row of pixel units; and the second side of each row of pixel units is provided with a second scanning line corresponding to the row of pixel units, and the second scanning line is connected to switch elements of second-type pixel units in the row of pixel units. An active layer structure of the switch element of a second-type pixel unit in an irow of pixel units has a common region with an active layer structure of the switch element of a first-type pixel unit in an (i+1)row of pixel units.

Array substrate and driving method thereof, display panel and display device

Disclosed are an array substrate and a display device. In some embodiments of the disclosure, at least one multi-access selector arranged proximate to a first non-right-angled edge is segmented into a plurality of sub-units, and orthographic projections of at least two of the sub-units are stagger in a Y direction, the Y direction is perpendicular to a X direction in which gate lines extend.

Array substrate and display device

An array substrate and a display panel are provided. The array substrate comprises a display area including a first and a second display area parallelly arranged along a first direction, wherein the second display area includes a first edge portion extending along a second direction; a non-display area including a first and a second non-display area, wherein in the second direction, the first non-display area is disposed at one side of the display area and includes a first sub-non-display area and a second sub-non-display area; at least one notch formed by recessing the first edge portion toward an inside of the second display area; data lines; and at least one driving chip. An orthogonal projection of the at least one driving chip onto the array substrate is at least partially located in the second sub-non-display area. The second non-display area is disposed at perimeter of the at least one notch.

Array substrate and display panel

Disclosed are an array substrate and a display device. In some embodiments of the disclosure, at least one multi-access selector arranged proximate to a first non-right-angled edge is segmented into a plurality of sub-units, and the sub-units are arranged in an extension direction of the first non-right-angled edge.

Provided is a display panel including a first substrate and a second substrate that are opposite to the first substrate and a sealant arranged in the non-display area. The first substrate includes a base substrate, first fanout wires and a planarization layer that are arranged at a side of the base substrate proximate to the second substrate. The first fanout wires are arranged in the non-display area and at a side of the planarization layer facing away from the base substrate. Each first fanout wire includes first to third wires that are connected in sequence. A distance between adjacent second wires is greater than a distance between adjacent first wires, and is greater than a distance between adjacent third wires. The planarization layer is provided with a first opening, and the first opening overlaps with the sealant and a second wire area formed by second wires.

The present disclosure provides an array substrate and a display panel. The array substrate includes a display area and a non-display area surrounding the display area. The display area includes a first corner, and data lines extending along a first direction and gate lines extending along a second direction are provided on the display area. The first direction intersects the second direction. The non-display area includes a first non-display area, a second non-display area and a first corner non-display area. The first corner non-display area is adjacent to the first and second non-display areas. The first corner non-display area is adjacent to the first corner. A data end circuit, a first signal line section and a first shift register are located in the first corner non-display area. The data end circuit is disposed at a side of the first shift register close to the display area.

Provided are a display panel, a display device, and a display panel control method. The display panel includes a display area and a non-display area. The non-display area includes a first area and a second area, and at least one first force-sensing sensor is provided in the first area and/or the second area. A plurality of touch electrodes and a plurality of touch signal lines respectively electrically connected to each of the touch electrodes are provided in the display area, and the touch signal lines include at least one multiplexed signal line respectively corresponding to each of the at least one first force-sensing sensor. The display area further includes at least one transverse connecting line. The display panel further includes at least one switch device, each of which and a corresponding transverse connecting line are connected in series between a corresponding first force-sensing sensor and a corresponding multiplexed signal line.

Display panel having touch electrodes and force sensors in periphery area and control method thereof

The present disclosure provides a display substrate, display panel, and display device. The display substrate includes: a base substrate having a display area and a periphery area surrounding the display area; a plurality of force sensors disposed in the periphery area; and a substrate layer layered upon the base substrate and disposed under a film layer where the plurality of force sensors are located and including a plurality of strip-shaped convex structures; wherein a portion of each of the plurality of force sensors corresponding to each of the plurality of strip-shaped convex structures is convex, and another portion of each of the plurality of force sensors corresponding to a gap between adjacent two of the plurality of strip-shaped convex structures is concave. The present disclosure achieves that abnormal display will not appear on display panel at display area edge or position corresponding to force sensor, thereby improving display effect.

Display substrate, display panel and display device

A display panel and a display device are provided. The display panel has a pixel region and a frame region surrounding the pixel region. The pixel region includes sub-pixels each including a first transistor and a pixel electrode. The plurality of sub-pixels includes display sub-pixels and dummy sub-pixels. At least part of the dummy sub-pixels are antistatic sub-pixels. A data line is configured to provide a driving signal to the display sub-pixels. A scan line is configured to provide scan signal to the display sub-pixels. A first reference signal line is configured to provide static protection reference signal to the antistatic sub-pixels. The first gate electrode of the first transistor of the antistatic sub-pixel is connected to the first drain electrode and a first reference signal line, and the first source electrode of the first transistor of the antistatic sub-pixel is connected to the data line.

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Xiamen, China

Hao Wu