Wisconsin Alumni Research Foundation

Hao Wang

Nam Sung Kim

Somesh Jha

A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.

Computer architecture having selectable parallel and serial communication channels between processors and memory

Computer architecture having selectable, parallel and serial communication channels between processors and memory

An architecture for improved memory access in asymmetric memories provides a set of shared row buffers that may be freely allocated between slow and fast memory banks of the asymmetric memory. This permits allocation of row buffers dynamically between the slow and fast memory banks to improve execution speeds and also permits a lightweight memory swap procedure for moving data between the slow and fast memory banks with low processor and memory channel overheads.

Shared row buffer system for asymmetric memory

A memory controller for heterogeneous computer processors dynamically adjusts access priorities by the different processors to maximize performance in the execution of a single parallel application program on both processor architectures. In one embodiment, the memory controller predicts sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences for improved implementation of the intended prioritization.

Memory controller for heterogeneous computer

A malware prevention system monitors kernel level events of the operating system and applies user programmable or preprepared policies to those events to detect and block malware.

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Madison, WI, United States of America

Hao Wang