International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Globalfoundries U.S. Inc.

Elpis Technologies Inc.

Hao Tang

Kangguo Cheng

Zhenxing Bi

Ruilong Xie

Cheng Chi

Hemanth Jagannathan

Lars W Liebmann

Chi-Chun Liu

Daniel Chanemougame

Yann A M Mignot

Mark V Raymond

Kisup Chung

Isabel C Estrada-Raygoza

Juntao Li

Chih-Chao Yang

Peng Xu

Theodorus E Standaert

Shogo Mochizuki

Michael Rizzolo

Injo Ok

Cornelius Brown Peethala

Yongan Xu

Nicole A Saulnier

Karen Elizabeth Petrillo

Dominik Metzler

Richard C Johnson

Lawrence Alfred Clevenger

Ekmini Anuja De Silva

Dongbing Shao

Shyng-Tsong Chen

Jing Guo

Jing Sha

One illustrative transistor device disclosed herein includes, among other things, a gate positioned above a semiconductor substrate, the gate comprising a gate structure, a conductive source/drain metallization structure positioned adjacent the gate, the conductive source/drain metallization structure having a front face, and an insulating spacer that is positioned on and in contact with at least a portion of the front face of the conductive source/drain metallization structure. In this example, the device also includes a gate contact opening that exposes at least a portion of the insulating spacer and a portion of an upper surface of the gate structure and a conductive gate contact structure positioned in the gate contact opening, wherein the conductive gate contact structure contacts at least a portion of the insulating spacer and wherein the conductive gate contact structure is conductively coupled to the gate structure.

Gate contact structure for a transistor device

Embodiments of the invention include methods and structures for controlling developer critical dimension (DCD) variations across a wafer surface. Aspects of the invention include an apparatus having developer tubing and an internal cam. The internal cam is coupled to a fixed axis. A flexible divider is positioned between the developer tubing and the internal cam. The flexible divider is coupled to the internal cam such that rotation of the internal cam about the fixed axis is operable to change an inner diameter of the developer tubing.

Developer critical dimension control with pulse development

A field effect transistor is provided. The field effect transistor includes a first source/drain on a substrate, a second source/drain on the substrate, and a channel region between the first source/drain and the second source/drain. The field effect transistor further includes a metal liner on at least three sides of the first source/drain and/or the second source/drain, wherein the metal liner covers less than the full length of a sidewall of the first source/drain and/or the second source/drain. The field effect transistor further includes a metal-silicide between the metal liner and the first source/drain and/or the second source/drain, and a conductive contact on the metal liner on the first source/drain and/or the second source/drain, wherein the conductive contact is a conductive material different from the conductive material of the metal liner.

Low capacitance low RC wrap-around-contact

In accordance with an embodiment of the present invention, a photolithographic mask is provided. The photolithographic mask includes at least one merged via pattern in the photolithographic mask for printing a merged via opening in a resist layer, wherein the at least one merged via pattern includes a compound shape having a first rectangular opening portion and a second rectangular opening portion that intersect at an angle.

Tight pitch via structures enabled by orthogonal and non-orthogonal merged vias

An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.

Alignment through topography on intermediate component for memory device patterning

A method for removing photoresist bridging defects includes coating a photoresist layer over a dielectric layer formed over a substrate, applying a first developer that results in formation of one or more photoresist bridging defects, and applying a second developer to remove the one or more photoresist bridging defects. The first developer is an aqueous base developer and the second developer is a reverse tone weak developer (RTWD), the RTWD being a mixture of a first (good) solvent and a second (bad) solvent for the photoresist.

Photoresist bridging defect removal by reverse tone weak developer

A capacitor includes a stack. The stack has a first metallic layer formed over a substrate, an insulator formed over the first metallic layer, and a second metallic layer formed over the insulator. The first metallic layer has at least one high domain and at least one low domain, where a surface of the substrate in the at least one low domain has a height that is lower than a surface of the substrate in the at least one high domain.

Efficient metal-insulator-metal capacitor

Methods are provided for patterning an active region formed in a semiconductor wafer. In one aspect, the methods generally include providing active regions and kerf regions between active regions in the semiconductor wafer, wherein the active regions and the kerf regions include a patterned dielectric layer, a metal conductor, and a liner layer between the dielectric layer and the metal conductor. An upper surface of the active regions and the kerf regions is planarized to form a planar surface. The metal conductor from the kerf regions is selectively removed to form a trench. An optically opaque layer is conformally deposited onto the semiconductor wafer to form a recessed alignment mark in the kerf regions. The active regions are then patterned using the recessed alignment mark in the kerf region.

Patterning integration scheme with trench alignment marks

A self-assembled heteroepitaxial oxide nanocomposite film including alternating layers of a first metal oxide having a first melting point and a second metal oxide having a second melting point that differs from the first melting point is formed in an opening formed in a semiconductor substrate. After forming a metal or metal alloy via structure in the semiconductor substrate, first and second thermal treatments are performed to remove each layer of first or second metal oxide providing a nanoporous membrane.

Method and structure to fabricate a nanoporous membrane

One device disclosed herein includes a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap, and conductive source/drain metallization structures adjacent the gate, each of the conductive source/drain metallization structures having a front face and a recess defined in each of the conductive source/drain metallization structures. In this example, the device further includes a spacer structure comprising recess filling portions that substantially fill the recesses and a portion that extends across a portion of the upper surface of the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, an insulating material within the spacer structure and on the exposed portion of the gate cap, a gate contact opening that exposes a portion of an upper surface of the gate structure, and a conductive gate contact structure in the conductive gate contact opening.

Gate contact structure for a transistor

Capacitors include a stack that has a first metallic layer formed over a substrate with at least one high domain and at least one low domain, an insulator formed over the first metallic layer, and a second metallic layer formed over the insulator. A bottom contact is formed in the substrate having a top surface that is even with a top surface of the substrate in the at least one high domain. A cap layer is formed directly on the substrate in the high domains, under the stack.

Techniques are provided for fabricating and utilizing optically opaque non-planar alignment structures in non-die areas (e.g., kerf areas) of a wafer to align photomasks to die areas on the wafer. For example, an insulating layer is formed over non-die and die areas of the wafer. A non-planar alignment feature is formed in the insulating layer in the non-die area. An optically opaque layer stack is formed in the die and non-die areas of the wafer, which conformally covers the non-planar alignment feature to form an optically opaque non-planar alignment structure in the non-die area. A lithographic patterning process is performed to pattern the optically opaque layer stack in the die area, wherein the optically opaque non-planar alignment structure in the non-die area is utilized to align a photomask to the die area. The optically opaque non-planar alignment structure can include any type of non-planar structure having a stepped sidewall surface.

Lithographic photomask alignment using non-planar alignment structures formed on wafer

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Slingerlands, NY, United States of America

Hao Tang