Other

Texas Instruments Corporation

G-2 Networks, Inc.

Hao Tang

Hung C Lin

Yang Liu

William Pierce Evans

Eric Naviasky

Anthony Caviglia

Tom P Broekaert

Patrick G Farrell

Sen-Jung Wei

Hugh Thompson

Shanlin Sun

Narisu Bai

John Ebner

Jan Paul Vander Wagt

A system and methods for automatically delineating OARs in whole-volume medical images through a two-stage DCNN model, the DCNN model comprising an OAR detection network and an OAR segmentation network, and the method comprising the steps of: inputting the whole-volume medical images to the OAR detection network; extracting image features through a sequence of downsampling blocks; generating a final detection feature map via upsampling and concatenation; detecting at least one OAR candidate by branching the final detection feature map, wherein the at least one OAR candidate is defined by a predicted bounding box with a class label; inputting the predicted bounding box and corresponding class label to the OAR segmentation network; cropping the final detection feature map and a downsampling block in the OAR detection network according to the predicted bounding box; concatenating the cropped feature maps and generating a predicted binary mask delineating OARs according to the class label.

Organs at risk auto-contouring system and methods

A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.

Clock recovery circuit

A high speed digital static shift register includes a series-connected pair of resonant tunneling diodes (RTDs) 22, 24 to achieve a bistable operating state. A clocked switch 20 provides the means of setting the binary state of this bistable pair. In order for one bistable pair to drive a following pair, a method of providing isolation and gain using a buffer amplifier 26 between the two pairs of RTDs is also provided. In one embodiment, the buffer amplifier comprises enhancement FET 30 and depletion load FET 28.

Ultra fast shift register using resonant tunnel diodes

A resonant tunneling diode stack used as a memory cell stack (X0-Xn) with sequential read out of bits of data cells (X1-Xn) by increasing ramp rates to transfer the stored bit to a lowest ramp rate cell (X0).

Resonant tunneling memory

The folding V-I characteristic of a resonant tunneling diode (RTD) is utilized to generate the multiple membership functions for each antecedent. The folding characteristic of an RTD generally has a triangular shape, which corresponds to the popular membership function functions commonly in use. The amount of overlap of adjacent membership functions can be adjusted by adding or substracting a dc current to or from the RTD characteristic. The use of RTD folding characteristic to generate multiple membership functions can be used in a fuzzifier to simplify circuit implementation. A time varying membership function can be generated by sweeping the RTD with a voltage ramp. This time varying membership function can be used in the defuzzifier to obtain a crisp output.

Fuzzy membership function generator using resonant tunneling diodes

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Silver Spring, MD, United States of America

Hao Tang