United Microelectronics Corp.

Hao Su

Hong Liao

Hang Hu

Chao Jiang

Chow Yee Lim

Yong-Liang Li

A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.

Semiconductor structure and method for forming the same

A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films above the floating gate, wherein each light-absorbing film is provided with at least one dummy via hole overlapping the floating gate, and a dielectric layer on each light-absorbing film and filling up the dummy via holes.

Light-erasable embedded memory device and method of manufacturing the same

A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least one light-absorbing film above the floating gate, wherein at least one light-absorbing film is provided with dummy via holes overlapping the floating gate, and a dielectric layer on the light-absorbing film and filling up the dummy via holes.

A vertical transistor device comprises a substrate, a first source, a drain, a first gate dielectric layer, a first gate electrode and a first doping region. The substrate has at least one protruding portion. The first source having a first conductivity type is formed on the substrate. The drain having the first conductivity type is disposed on the protruding portion. The first gate electrode is disposed adjacent to a first sidewall of the protruding portion. The first gate dielectric layer is disposed between the first gate electrode and the first sidewall as well as being disposed adjacent to the first source and the drain. The first doping region having a second conductivity type is formed beneath the protruding portion and adjacent to the first source.

Vertical transistor device with halo pocket contacting source

The present invention provides a method of forming a doping region. A substrate is provided, and a poly-silicon layer is formed on the substrate. A silicon oxide layer is formed on the poly-silicon layer. An implant process is performed to form a doping region in the poly-silicon layer. The present invention further provides a method for forming a MOS.

Method for forming doping region and method for forming MOS

A method for forming an embedded capacitor structure is provided. Firstly, a first dielectric layer having a trench therein on a substrate is provided. A capacitor structure is formed on the bottom surface of the trench. The capacitor structure includes a first metal layer, a capacitance-insulating layer and a second metal layer and the portion surface of the first metal layer on the bottom surface of the trench is exposed. A cap layer is formed on the top surface and the inner surface of the trench and on the capacitor structure. A second dielectric layer is formed on the cap layer. The portion of second dielectric layer and the portion of the cap layer are removed to form a plurality of contact windows therein, and the portion surface of the first metal layer and the portion surface of the second metal layer are exposed by the plurality of contact windows.

Embedded capacitor structure and the forming method thereof

A manufacturing method of a semiconductor device includes the following steps. First, a substrate is provided. At least one gate trench and a first inter-layer dielectric layer are formed on the substrate. A work function metallic layer is then formed in the gate trench. A first contact hole is then formed in the first inter-layer dielectric layer. A main conductive layer is formed in the gate trench and the first contact hole simultaneously.

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Singapore, Singapore

Hao Su