Yangtze Memory Technologies Co., Ltd.

Hao Pu

Qiguang Wang

Tuo Li

Lei Li

JinHao Li

Yingjie Zhao

Caiyu Wu

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a layer stack, a channel hole, a blocking layer, a charge trap layer, a tunnel insulation layer, and a channel layer. The surface region of the charge trap layer includes a carbon region that contains a certain amount of carbon elements.

Three-dimensional memory device with charge trap layer including carbon region and fabrication method thereof

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a dielectric stack over a substrate, forming a functional layer and a semiconductor channel through the dielectric stack, forming a conductor/insulator stack based on the dielectric stack, and forming memory cells through the conductor/insulator stack. Each memory cell includes a portion of the functional layer and the semiconductor channel. At least one of the functional layer and the semiconductor channel includes a certain amount of deuterium elements.

Three-dimensional memory device and fabrication method for enhanced reliability

Semiconductor fabrication methods and semiconductor devices are disclosed. According to some aspects, a memory device includes a memory stack having interleaved a plurality of conductive layers and a plurality of insulating layers on a substrate, and a channel structure extending vertically in the memory stack. The channel structure includes a semiconductor channel extending vertically in the memory stack and conductively connected to a source structure. The semiconductor channel includes polysilicon, and a grain size of the polysilicon ranges from 100 nm to 600 nm.

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Wuhan, China

Hao Pu