Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Semiconductor Manufacturing International Corp.

Hao Ni

Yi Jin Kwon

Tao Wang

Yao Zhou

Chuntian Yu

Hong Yu

Guangyan Luo

Tian Shen Tang

Yu Cheng

Xiaoyan Liu

Tengye Wang

Xiao Liu

Xiao Mei Zheng

Jiaxu Peng

Zijian Zhao

Siwen Zheng

Yijin Kwon

Changwei Yin

Dan Ning

Zi Jian Zhao

Jim Chia-Ming Hsu

Chang Wei Yin

Jia Xu Peng

Tianshen Tang

A magnetic memory and its programming control method and reading method, and a magnetic storage device of the magnetic memory are provided in the present disclosure. The magnetic memory includes a first magnetic tunnel junction memory cell, including a first terminal coupled to a first bit line, and further includes a switch device, including a first terminal coupled to a second terminal of the first magnetic tunnel junction memory cell, and a control terminal connected to a switch control signal. The magnetic memory further includes a second magnetic tunnel junction memory cell, including a first terminal coupled to a second bit line, and a second terminal coupled to a second terminal of the switch device. The magnetic memory further includes a first transistor, a second transistor, and a sensing amplifier.

Magnetic memory, and programming control method, reading method, and magnetic storage device of the magnetic memory

Readout circuit and magnetic memory are provided. The readout circuit includes a first charging capacitor with one end grounded and another end coupled to an output of a data unit; a first pre-charge module for charging the first charging capacitor; a first discharge control module for controlling a magnitude of a data voltage; a second charging capacitor with one end grounded and another end coupled to an output of a reference unit; a second pre-charge module for charging the second charging capacitor; a second discharge control module for controlling a magnitude of a reference voltage; and a sense amplifier for outputting readout signals.

Readout circuit of magnetic memory and magnetic memory

A data reading circuit and a storage unit are provided. The data reading circuit includes a being read unit, a reference current generation unit, a current adjustment unit, a reference unit, a comparison unit, and a voltage stabilization unit corresponding to the reference unit. The being read unit is connected to the current adjustment unit and the comparison unit. The reference current generation unit is connected to the current adjustment unit. The current adjustment unit is connected to the reference current generation unit, the being read unit, and the comparison unit. The reference unit is connected to the voltage stabilization unit. The comparison unit is connected to the voltage stabilization unit, the being read unit, and the current adjustment unit. The voltage stabilization unit is connected to the reference unit and the comparison unit.

Data reading circuit and storage unit

A non-volatile memory (NVM) includes at least one memory unit region, each including a memory array and having first memory cells in the odd columns and second memory cells in the even columns. Corresponding to each memory unit region, the NVM includes a multiplexer including first bit line decoders and second bit line decoders, a comparator circuit including a first input terminal and a second input terminal, and a bias generation circuit generating a bias voltage. When reading a data information from a first memory cell, a first output voltage of the first memory cell is sent to the first input terminal and the bias voltage is sent to the second input terminal. When reading a data information from a second memory cell, a second output voltage of the second memory cell is sent to the second input terminal and the bias voltage is sent to the first input terminal.

Non-volatile memories and data reading methods thereof

A high voltage level shifting circuit and related semiconductor devices are presented. The circuit comprises: a level conversion circuit that converts an input signal with a first high voltage to an output signal with a second high voltage; a first switch having a first node connected to a first power source and a second node connected to a control node of a first transistor; a second switch having a first node connected to the control node of the first transistor and a second node connected to a first connection node; and a switch control circuit connected to the first switch and the second switch and controls them not to be close at the same time. By adding these two switches to the level conversion circuit, this inventive concept substantially lowers the static current generated during a high voltage level conversion process.

High voltage level shifting (HVLS) circuit and related semiconductor devices

Memory arrays and reading, programming and erasing methods of the memory arrays are provided. An exemplary memory array includes a plurality of memory columns. Each memory column has a plurality of flash memory cells. The memory columns are divided into at least two blocks. At least one source pull down column is disposed between the two adjacent blocks. Each source pull down column has a plurality of flash memory cells. A source of each flash memory cell in the source pull down column is coupled to sources of the flash memory cells of the plurality memory columns in a same row as the flash memory cell in the source pull down column to pull down a source of a selected flash memory cell to 0 V.

Memory array, and method for reading, programming and erasing memory array

A memory decoding system includes a memory decoding reference current module. The memory decoding reference current module includes: a first reference current unit connected to one end of a second reference bit line; a second reference current unit connected to one end of a first reference bit line; a third reference current unit connected to one end of a third reference bit line; a first reference NMOS transistor, a source of which is connected to the second reference bit line; a second reference NMOS transistor, a source of which is connected to a drain of the first reference NMOS transistor; and a gate of the first reference NMOS transistor and a gate of the second NMOS transistor are connected to a logic high level.

Memory decoding system

A nonvolatile memory includes a first array bank coupled to a first bit-line, a second array bank coupled to a second bit-line, a pre-charging circuit, a first selection circuit, a second selection circuit, and a sense amplifier. An address enable signal sent to the first selection circuit controls whether the pre-charging circuit needs to pre-charge the first bit-line and the second bit-line. The sense amplifier is configured to compare a first voltage from the first output terminal of the pre-charging circuit with a second voltage from the second output terminal of the pre-charging circuit to obtain a result indicating data information stored in the first array bank or in the second array bank. The second selection circuit is configured to connect a reference current to the first input terminal or the second input terminal of the sense amplifier based on a first word-line signal and a second word-line signal.

Nonvolatile memories and reading methods thereof

A charge pump voltage regulator is provided. The charge pump voltage regulator includes a charge pump circuit, where an output terminal of the charge pump circuit outputs a stable voltage. The charge pump voltage regulator also includes a voltage divider circuit suitable to divide the stable voltage to output a divided voltage and a clock oscillator providing a drive clock signal for the charge pump circuit. In addition, the charge pump voltage regulator includes a first voltage comparator circuit suitable to output at least one of a first comparison result and a second comparison result. Further, the charge pump voltage regulator includes a logic control unit, where, when the charge pump voltage regulator operates in a standby mode, the logic control unit outputs a first control level to the clock oscillator according to the at least one of the first comparison result and the second comparison result.

Charge pump voltage regulator

A memory and a reference circuit calibration method are provided. The memory includes: a memory array including a plurality of memory cells; a reference circuit including a reference memory cell and a reference connection terminal, wherein the reference memory cell is a same as the memory cell; a calibration circuit including a calibration connection terminal, and a mirror circuit including a first mirror terminal and a second mirror terminal, wherein the first mirror terminal is connected to the reference connection terminal, and the second mirror terminal is connected to the calibration connection terminal; a clamp circuit, configured to set one of a voltage of the reference connection terminal and a voltage of the calibration connection terminal as a preset voltage and to set the other thereof as a comparison voltage; and a comparison circuit configured to input the comparison voltage and the preset voltage, and to output a comparison result.

Memory and reference circuit calibration method thereof

A word line voltage generator circuit, a semiconductor device, and an electronic device are provided. The word line voltage generator circuit includes a switch circuit connected to a high-level signal and a low-level signal and configured to output the high-level signal or the low-level signal as a word line voltage signal based on an input signal, and a drive signal control circuit configured to provide a drive signal connected to the switch circuit in response to the input signal. A voltage rising speed of the word line voltage signal is controlled by the drive signal.

Word line voltage generator for multiple-time programmable memory

A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor.

Memory device, related method, and related electronic device

The present disclosure provides control methods and control apparatus thereof and reference current modules of memory decoding systems. An exemplary control method of a memory decoding system comprising a decoder having at least a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a fourth NMOS transistor, a memory cell, and at least a first bit line and a second bit line, includes applying a first control signal, being at a logic low level during a first read operation stage of a read operation and at a logic high level during a second read operation stage after the first read operation stage of the read operation, to a gate of the first PMOS transistor; applying a second control signal to a gate of the second PMOS transistor; and applying a fourth control signal to a gate of the first NMOS transistor.

Control method and control apparatus of memory decoding system

A high voltage level shifter includes a first high-voltage P-channel metal oxide semiconductor (HVPMOS) transistor, a second HVPMOS transistor, a discharge transistor having a first native high-voltage N-channel metal oxide semiconductor (HVNMOS) transistor and a first low-voltage N-channel metal oxide semiconductor (LVNMOS) transistor connected in series, and an avalanche transistor having a second HVNMOS transistor and a second LVNMOS transistor connected in series.

High voltage level shifter in ultra low power supply memory application

A selected gate (SG) driver circuit, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor. A gate electrode of the first NMOS transistor is connected to a gate electrode of the first PMOS transistor, a source electrode of the first NMOS transistor being connected to a drain electrode of the third NMOS transistor, and a drain electrode of the first NMOS transistor being connected to a drain electrode of the first PMOS transistor and a gate electrode of the second NMOS transistor. A source electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, and a drain electrode of the second NMOS transistor being connected to a drain electrode of the second PMOS transistor and a gate electrode of the third NMOS transistor.

Growing community of inventors

Shanghai, China

Hao Ni