Sandisk Technologies Inc.

Sandisk Corporation

Micron Technology Incorporated

Hao Nguyen

Man Lung Mui

Seungpil Lee

Jongmin Park

Deepak Chandra Sekar

Yingda Dong

Nima Mokhlesi

Juan Lee

Hock C So

Shahzad Khalid

Khanh Vinh Nguyen

Fanglin Zhang

Prashanti Govindu

Chi-Ming Wang

Toru Ishigaki

Aaron S Yip

Gerrit Jan Hemink

Chang Hua Siau

Ken Oowada

Tomoko Ogura Iwasaki

Yoshihiko Kamata

Dheeraj Srinivasan

Erwin E Yu

Lawrence Celso Miranda

Sheyang Ning

Amul Dhirajbhai Desai

Jong Park

Dengtao Zhao

Mohan Dunga

Changyuan Chen

Tien-Chien Kuo

Yuki Mizutani

Ohwon Kwon

Kenneth Louie

Sung-En Wang

Tapan Samaddar

Yosuke Kato

Yee Lih Koh

Masahide Matsumoto

Chia-Kai Chou

Greg Goldey

Moutaz Elkaissi

Alexander Tsang-Nam Chu

Vamsi Krishna Sakhamuri

Robert Jv Jackson

Man Lung Lui

Tianhua Zhang

Jorge Sotelo

Wendell Blackman

Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.

Memory devices with four data line bias levels

Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

Memory cell sensing

Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. By allowing the sense amplifier to bias a memory cell being sensed to a selected one of multiple bias levels during a sensing operation, multiple target data states can be concurrently program verified, leading to higher performance when writing data.

Concurrent multi-state program verify for non-volatile memory

A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. To reduce noise, a decoupling capacitor is connected to the control gate of the discharge transistor and an auxiliary keeper current is run through the discharge transistor.

Sense amplifier with negative threshold sensing for non-volatile memory

The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics&#x2014;e.g., gate width and gate length dimensions&#x2014;of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.

Voltage generator to compensate for process corner and temperature variations

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Techniques for programming of select gates in NAND memory

In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs.

Segmentation of blocks for faster bit line settling/recovery in non-volatile memory devices

In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.

Utilizing NAND strings in dummy blocks for faster bit line precharge

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

Compact high speed sense amplifier for non-volatile memory with reduced layout area and power consumption

Rather than supply an internal node of a non-volatile memory's sense amplifier from a supply level through a transistor by applying a voltage to the transistor's gate to clamp the node, the internal node is supplied by an op-amp through a pass gate. The op-amp receives feedback from above the pass gate. This allows a desired voltage level to be more quickly and accurately established on the node. Using a two-step reference level for the op-amp can further increases speed and accuracy. Biasing the op-amp with the external power supply can offer additional advantages.

Operational amplifier methods for charging of sense amplifier internal nodes

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp includes a latch, which is connected to a data bus, and bit line selection circuitry by which it can selectively be connected to one or more bit lines. The sense amp also includes some intermediate circuitry having a first node connectable to a selected bit line through the bit line selection circuitry and a second node that is connectable to the latch circuit. The sense amp can include switches where the second node can be connected to either the value held in the latch or the inverse of the value held in the latch. The sense amp can also include a switch where an internal node of the sense amp can be connected directly to a voltage supply level.

Compact high speed sense amplifier for non-volatile memory

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San Jose, CA, United States of America

Hao Nguyen