Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Hao-Ming Lien

Chih-Tang Peng

Tze-Liang Lee

Chao-Cheng Chen

Pei-Ren Jeng

Kuo-Tai Huang

Yi-Hung Lin

Bing-Hung Chen

Wei-Che Hsieh

Cheng-Hsing Hsu

Syun-Ming Jang Jang

Chii-Horng Li

Chih-Han Lin

Hang-Ting Lue

Tai-Chun Huang

Ming-Hua Yu

Chia-Wei Chang

Mong-Song Liang

Chien-Hao Chen

Harry Chuang

Yu Chao Lin

Chyi Shyuan Chern

Chu-Yun Fu

Jin-Aun Ng

Chien-Liang Chen

Jun-Lin Yeh

Kang-Cheng Lin

Wen-Chih Yang

Shiang-Rung Tsai

Jui-Hei Huang

Yu-Ling Liou

Chi Hsin Chang

Chun Ming Lin

Brian Wang

Yu-Lien Huang

Chao-I Wu

Hun-Jan Tao

Ryan Chia-Jen Chen

Ming-Hsi Yeh

Ming-Hsiu Lee

Ling-Yen Yeh

Yih-Ann Lin

Chun-Hung Lee

Jr Jung Lin

Ming-Hsiang Hsueh

Weibo Yu

Chung-Hau Fei

Ssu-Yi Li

Chang-Shen Lu

Tai-Chung Huang

Ssu-Yu Li

Chien-Hau Fei

Kai-Ting Tseng

An injector for forming films respectively on a stack of wafers is provided. The injector includes a plurality of hole structures. Every adjacent two of the wafers have therebetween a wafer spacing, and each of the wafers has a working surface. The hole structures respectively correspond to the respective wafer spacings. The working surface and a respective hole structure have therebetween a parallel distance. The parallel distance is larger than a half of the wafer spacing. A wafer processing apparatus and a method for forming films respectively on a stack of wafers are also provided.

Injector for forming films respectively on a stack of wafers

An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.

Semiconductor strips with undercuts and methods for forming the same

In an embodiment, a method includes: patterning a plurality of mandrels over a mask layer; forming an etch coating layer on top surfaces of the mask layer and the mandrels; depositing a dielectric layer over the mask layer and the mandrels, a first thickness of the dielectric layer along sidewalls of the mandrels being greater than a second thickness of the dielectric layer along the etch coating layer; removing horizontal portions of the dielectric layer; and patterning the mask layer using remaining vertical portions of the dielectric layer as an etching mask.

Semiconductor device and method

A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.

Fin deformation modulation

A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively.

Uniform shallow trench isolation regions and the method of forming the same

A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.

Dummy FinFET structure and method of making same

A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.

Strained isolation regions

An isolation region gap fill method comprises depositing a first dielectric material over a semiconductor device through a flowable deposition process or other gap fill deposition processes, wherein the semiconductor device includes a first FinFET comprising a plurality of first fins and a second FinFET comprising a plurality of second fins. The method further comprises removing the first dielectric material between the first FinFET and the second FinFET to form an inter-device gap, depositing a second dielectric material into the inter-device gap and applying an annealing process to the semiconductor device.

Isolation region gap fill method

A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.

Semiconductor device and method of manufacture

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Hsinchu, Taiwan

Hao-Ming Lien