Maxlinear, Inc.

Hao Liu

Yongjian Tang

Methods and systems for charge compensation for switched-capacitor circuits may comprise, in an electronics device comprising a first voltage source, a switched capacitor load, and a switched capacitor compensation circuit: switching a capacitor in the switched capacitor load from a first voltage to a second voltage; providing a charge to the switched capacitor load from the switched capacitor compensation circuit without requiring added charge from the first voltage source. A reference voltage may be generated utilizing the first voltage source. A replica reference voltage for the switched capacitor compensation circuit may be generated utilizing a second voltage source. The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device. Capacitors may couple outputs of the first and second voltage sources to ground.

Method and system for charge compensation for switched capacitor circuits

Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each input line to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2where x ranges from 0 to m&#x2212;1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than V/128+V/256+V/512+V/1024 when m equals 4 and where Vis the full-scale voltage of the ADC.

Method and system for an analog-to-digital converter with near-constant common mode voltage

Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2where x ranges from 0 to m&#x2212;1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than V/128+V/256+V/512+V/1024 when m equals 4 and where Vis the full-scale voltage of the ADC.

Methods and systems for an analog-to-digital converter (ADC) with constant common mode voltage may include in an ADC comprising a sampling switch on a first input line to the ADC, a sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on the first input line, and N switched capacitor pairs and M single switched capacitors on the second input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels, and iteratively switching the single switched capacitors between ground and voltages that are a fraction of Vref, which may equal Vref/2where x ranges from 0 to m&#x2212;1 and m is a number of single switched capacitors per input line.

Method and system for charge compensation for switched-capacitor circuits

Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2where x ranges from 0 to m&#x2212;1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than V/128 +V/256+V/512+V/1024 when m equals 4 and where Vis the full-scale voltage of the ADC.

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Carlsbad, CA, United States of America

Hao Liu