Qualcomm Incorporated

Regor Pharmaceuticals, Inc.

Hao Liu

Dong Ren

Li Hsiang Sun

Yu Song

Miao Li

Daisuke Terasawa

Deepu John

Sivarama Krishnan Venkatesan

Qiuzhen (Joe) Zou

Bohuslav Rychlik

Wei Huang

Zhi Zhu

Wenge Zhong

Lejie Lu

Wesley James Holland

Xiaotian Zhu

Zhiqin Chen

Andrew Edmund Turner

Song Feng

Hua Zhou

Hongmei Liao

Sudheer Chowdary Gali

Lei Wu

Kate Xin Wen

Rongqiang Liu

Aspects of a charge pump with reduced leakage current are disclosed. An apparatus includes a main branch having two parallel lines of switches and a main branch output, a side branch coupled to the main branch having two parallel lines of switches and a side branch output and a charge pump output at which the main branch output and the side branch output are coupled together.

Charge pump for phase locked loop with reduced leakage current

A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.

Fast locking dual loop clock and data recovery circuits

A voltage controlled oscillator (VCO), including: at least one second upper voltage rail; at least one second lower voltage rail; a ring of N cascaded inverters, wherein the set of N cascaded inverters are coupled between the at least one second upper voltage rail and the at least one second lower voltage rail; at least one first frequency band select circuit coupled between first upper voltage rail and the at least one second upper voltage rail; at least one second frequency band select circuit coupled between the at least one second lower voltage rail and first lower voltage rail; at least one first VCO frequency control circuit coupled between the first upper voltage rail and the at least one second upper voltage rail; and at least one second VCO frequency control circuit coupled between the at least one second lower voltage rail and the first lower voltage rail.

Wideband rail-to-rail voltage controlled oscillator

A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.

Analog receiver front-end with variable gain amplifier embedded in an equalizer structure

An amplifier has a first amplifying circuit configured to receive a voltage input and to output an amplified current, a second amplifying circuit configured to receive the amplified current and to output an amplified voltage, the second amplifying circuit comprising a pair of feedback resistive elements, each feedback resistive element being coupled to a gate and drain of a corresponding transistor in a pair of output transistors in the second amplifying circuit, and a feedback circuit configured to provide a negative feedback loop between an input and an output of the pair of output transistors, the feedback circuit including a first transconductance amplification circuit and a first equalizing circuit.

Ultra-high bandwidth inductorless amplifier

A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.

Circuits and methods for maintaining gain for a continuous-time linear equalizer

Certain aspects are directed to an amplifier. The amplifier generally includes a first transistor having a gate coupled to an input node of the amplifier, a source degeneration circuit, and a second transistor coupled between the source degeneration circuit and a source of the first transistor, a gate of the second transistor being configured to receive a gain control signal from a controller.

Variable gain amplifier with embedded equalization for uniform tuning

A clock system including: an in-phase clock input and an in-phase clock output; a quadrature clock input and a quadrature clock output; a control loop configured to receive the in-phase clock output and the quadrature clock output, the control loop including a Boolean logic gate coupled to an operational amplifier (op-amp) through a low-pass filter; and an analog delay element coupled between the quadrature clock input and the quadrature clock output, the analog delay element comprising a plurality of capacitors.

Systems and methods for reduction of in-phase and quadrature-phase (IQ) clock skew

Systems and methods for managing coherency in a processing system comprising a memory involve one or more aperture cache coherency (ACC) blocks. The ACC blocks monitor accesses to the memory using aliased addresses, wherein the aliased addresses map to locations in an aliased address domain of the memory. The ACC blocks also monitor accesses to the memory through a functional address aperture using aperture addresses, wherein a function of the aperture addresses map to locations in an aperture address domain of the memory. The ACC blocks are further configured to maintain coherency between one or more of data in a first location of the memory, the first location belonging to the aliased address domain and the aperture address domain; one or more copies of the data accessed using the aperture addresses; or one or more copies of the data accessed using the aliased addresses.

Cache coherence with functional address apertures

Techniques for efficient searching in asynchronous systems, such as W-CDMA, as well as multi-mode searching, are disclosed. In one aspect, step one and step three search are performed in a single search engine. In another aspect, a search engine is configurable to search the offsets of a slot in step one search, producing sequential hypothesis energies, and peak detecting and sorting those energies. In yet another aspect, the peak detector and sorter are configurable to perform step one searching or step three/multimode searching. Various other aspects of the invention are also presented. These aspects have the benefit of circuit area and search-time efficiency which translate into reduced costs, increased standby time, increased acquisition speed, higher quality signal transmission, increased data throughput, decreased power, and improved overall system capacity.

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San Diego, CA, United States of America

Hao Liu