Cadence Design Systems, Inc.

Hao Ji

Donald John O'Riordan

Taber H Smith

Joseph Michael Swenton

Jun Chen

Li J Song

Rachid Salik

Raja Mitra

Abdelhakim Bouamama

Zhan-Zhong Yao

An approach is described for efficient and accurate signal electromigration analysis of digital-on-top designs with complex interface pin shapes. According to some embodiments, the approach includes performance of parasitic analysis for the interface between nets and primitive/macro cell (blocks). Specifically, the approach includes performing parasitic analysis based on actual location information corresponding to overlap/connection between ports within blocks, external net connections to the ports, and internal net (block net) connections to the port. Thus, by determining the actual locations of the connections (as opposed to a presumed location) the parasitic effects associated with the ports and the connections thereof can be calculated.

Method and apparatus for efficient and accurate signal electromigration analysis of digital-on-top designs with complex interface pin shapes

An apparatus and method for visualizing faults in a circuit design includes simulating faults for a circuit design in a layout and a schematic, editing the layout and schematic to include the simulated fault, and linking the layout and schematic with the fault simulation.

Analog fault visualization system and method for circuit designs

A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography.

Method and system performing block-level RC extraction

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San Jose, CA, United States of America

Hao Ji