Advanced Micro Devices Corporation

Other

Fujitsu Corporation

Spansion Llc.

Sandisk Corporation

Advance Micro Devices, Inc.

Fujitsu Amd Semiconductor Limited

Hao Fang

John JianShi Wang

Mark S Chang

Narbeh Derhacobian

Kent Kuohua Chang

Masaaki Higashitani

King Wai Kelwin Ko

Sameer S Haddad

Lu You

Maria Chow Chan

Pau-Ling Chen

Michael K Templeton

Timothy J Thurgate

Yue-Song He

Peng Fang

Kenneth Wo-Wai Au

Michael K Han

Angela Tai Hui

George Matamis

Tuan Duc Pham

Chi K Chang

Henry Chien

Todd P Lukanc

John T Yue

Tho Le La

David K Liu

Wenge Yang

Guarionex Morales

Binghe Wang

Nader A Radjy

David H Chi

Kelwin Ko

Salvatore F Cagnina

Jianshi Wang

K Michael Han

Judith Quan Rizzuto

Ken Au

Chris Schmidt

Mike Templeton

Narbeh Derhocobian

Massaki Higashitani

Maria Chow-Chan

Bill Cox

Xingming Gao

Wenqian Yang

Jun Yan

Masaatzi Higashitani

Toru Ishigaki

Farrokh Omid-Zehoor

A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

Method and system for providing contact to a first polysilicon layer in a flash memory device

Described herein are boronic acid fluorescent compounds and methods of use thereof.

Water soluble boronic acid fluorescent reporter compounds and methods of use thereof

A NAND flash memory structure and method of making a flash memory structure with shielding in the bitline direction as well as in wordline and diagonal directions from Yupin effect errors and from disturbs.

Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory

In a first aspect of the present invention, a method of fabricating a flash memory device is disclosed. The method comprises the steps of providing a portion of a dual gate oxide in a periphery area of the memory device and then simultaneously providing a dual gate oxide in a core area of the memory device and completing the dual gate oxide in the periphery area. Finally, a nitridation process is provided in both the core and periphery areas subsequent to the previous steps. In a second aspect of the present invention, a flash memory device is disclosed. The flash memory device comprises core area having a plurality of memory transistors comprising an oxide layer, a first poly layer, an interpoly dielectric layer, and a second poly layer. The flash memory device further comprises a periphery area having a plurality of transistors comprising an oxide layer, a portion of the first poly layer, and the second poly layer. According to the present invention, the method for fabricating the flash memory device is a simplified process that results in a significant improvement in the oxide reliability in the core and periphery areas and also eliminates the nitrogen contamination problem in the periphery area.

Flash memory device and a method of fabrication thereof

A flash memory array having improved core field isolation in select gate regions via shallow trench isolation and field isolation implant after liner oxidation is disclosed. The flash memory array includes a core area and a periphery area, wherein the core area further includes a select gate region. The method of fabricating the flash memory array begins by patterning a layer of nitride over a substrate in active device locations. After the nitride is patterned, a silicon trench etch is performed to form trenches. After forming the trenches, a layer of liner oxide is grown in the trenches. Then, a field implant is performed in both the core area and periphery area to provide field isolation regions for the flash memory array with. Thereafter, poly1 is patterned in the core area to form floating gate and select word-lines.

Flash memory having improved core field isolation in select gate regions

A method of forming a NAND-type flash memory device including forming a stacked gate flash memory structure ( ) containing an interpoly dielectric layer ( ) for one or more flash memory cells in a core region ( ). The method also includes forming a select gate transistor structure ( ) having a first gate oxide ( ) formed of the interpoly dielectric material and a gate conductor ( ) overlying the first gate oxide ( ) in the core region ( ). A NAND-type flash memory device includes a core region ( ) comprising a stacked gate flash memory cell structure ( ) and a select gate transistor ( ) and a periphery region ( ) comprising a low voltage transistor ( ) and a high voltage transistor ( ). The stacked gate flash memory cell structure ( ) includes a tunnel oxide layer ( ), a poly layer ( ) overlying the tunnel oxide layer ( ), an interpoly dielectric layer ( ) formed of an insulating material overlying the poly layer ( ) and a poly layer ( ) overlying the interpoly dielectric layer ( ). In addition, the select gate transistor structure ( ) includes a gate insulator ( ) formed of the insulating material and a poly layer ( ) overlying the gate insulator ( ).

NAND type core cell structure for a high density flash memory device having a unique select gate transistor configuration

The present invention is a method and system for processing a semiconductor device, the semiconductor device comprising at least two gate stacks and a spacer gap. The method and system comprise utilizing a spin-on technique at the transistor device level to provide an oxide spacer in the spacer gap and then curing the semiconductor device at a temperature above approximately 450&deg; C. Through the use of a system/method in accordance with the present invention, the voids that are created in the spacer gaps during conventional semiconductor processing are eliminated. Furthermore, the oxide spacers posses the high quality characteristics that are typically provided through the use of the conventional CVD methodology. Accordingly, as a result of the use of the system/method in accordance with the present invention, the MOSFET oxide spacers are strengthened, which increases the reliability of the semiconductor device.

Method and system for processing a semiconductor device

In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array further comprises shallow trenches in the substrate, each of the shallow trenches including a layer of oxide, the layer of oxide having a top surface, wherein the top surface of the layer of oxide and the top surface of the layer of nitride are on substantially the same plane and channel areas wherein the occurrences of polyl stringers in the channel areas is substantially reduced. In a second aspect of the present invention, a method and system for fabricating a flash memory array is disclosed. The method comprises the steps of providing a layer of nitride over a substrate, forming trenches in the substrate and then growing a layer of oxide in the trenches. Finally, the layer of oxide is polished back. Through the use of the preferred embodiment of the present invention, a shallow trench isolation process is implemented as opposed to LOCOS process, thereby reducing the occurrence of polyl stringers in the channel area. Accordingly, the occurrence of unwanted electrical shorting paths between the adjacent regions is substantially reduced.

Flash memory array and a method and system of fabrication thereof

A system and method detecting the presence of polysilicon stringers on a memory array using a polysilicon stringer monitor. The polysilicon stringer monitor includes a continuous type-2 layer of polysilicon forming a first row and a second row across the active region and covering the active region in-between the first and second rows. The polysilicon stringer monitor further includes a continuous type-1 layer of polysilicon extending under the first row, wherein the type-1 layer also covers the active area in-between the first and second rows as well as covers the active area under the second row.

Method and system for providing a polysilicon stringer monitor

A method and system for providing an alignment mark for a thin layer in a semiconductor device is disclosed. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system include providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system include providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also include removing a portion of the at least one alternative part to provide the alignment mark in the at least one alternative part.

Method and system for providing a robust alignment mark at thin oxide layers

A method of manufacturing a high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect while avoiding an excessive number of costly masking steps. A high gated diode breakdown voltage is provided in the manufacturing process by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Method of manufacturing high voltage transistor with modified field implant mask

A method and system for providing a plurality of lines in a semiconductor memory device is disclosed. The method and system include providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask. The method and system also preferably include removing a second portion of the layer of material exposed by the pattern of the physical mask to form the plurality of lines.

Method for improved control of lines adjacent to a select gate using a mask assist feature

A semiconductor device having reduced field oxide recess and method of fabrication is disclosed. The method of fabricating the semiconductor device begins by performing an HF dip process on a substrate after field oxidation followed by performing a select gate oxidation. Thereafter, a core implant and a field implant are performed. After the implants, a tunnel oxide mask is deposited. The select gate oxide is then etched in areas uncovered by the tunnel oxide mask, and tunnel oxidation is performed.

Semiconductor device having reduced field oxide recess and method of fabrication

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Cupertino, CA, United States of America

Hao Fang