National Yang Ming Chiao Tung University

TSMC Solid State Lighting Ltd.

Epistar Corporation

National Applied Research Laboratories

Lite-on Technology Corporation

Academia Sinica

Other

Hon Hai Precision Industry Co., Ltd.

Lite-on Opto Technology (changzhou) Co., Ltd.

Sino-american Silicon Products Inc.

Yuan Licensing Co., Ltd.

Hao-Chung Kuo

Zhen-Yu Li

Hsing-Kuo Hsia

Tien-Chang Lu

Shing-Chung Wang

Ching-Hua Chiu

Jia-Min Shieh

Kuan-Chun Chen

Ming-Hua Lo

Bau-Tong Dai

You-Da Lin

Chun-Yen Chang

Hung-Wen Huang

Wen-Hsien Huang

Chang-Hong Shen

Jung Yan Huang

Yuh-Jen Cheng

Chao-Hsun Wang

An-Jye Tzou

Chung-Pao Lin

Hsin-Chieh Huang

Wen-Ching Hsu

Kuo-Ju Chen

Chun-Yen Peng

Kuo-Ming Chiu

Meng-Sung Chou

Ci-Ling Pan

Chia-Hua Chang

Da-Wei Lin

Chih-Ming Lai

Pei-Chen Yu

Hon-Way Lin

Chien-Chung Lin

Cheng-Hung Wei

Bo-Wen Lin

Chao-Cheng Ting

Huei-Min Huang

Cindy Huichun Shu

Ching-Yen Peng

Shih-Chuan Wu

Wen-Chein Yu

Che-Yu Liu

Chao-Kei Wang

Jung-Y Huang

Hau-Vei Han

Chin-Sheng Yang

Shih-Wei Chen

Chunyen Chang

Wen-Chien Miao

Shih-Chen Chen

Hsin Chiang

Chia-Yu Lee

Fu-He Hsiao

Chen-Yu Li

A micro LED display device includes a light emitting layer, a color conversion layer located on a light emitting surface of the light emitting layer, and a Bragg reflection element located on the color conversion layer. The Bragg reflection element includes a plurality of layer pairs. Each of the layer pairs includes at least one first layer and at least one second layer alternately stacked. The layer pairs include a top layer pair, a bottom layer pair and a plurality of middle layer pairs between the top layer pair and the bottom layer pair. A thickness of the first layer of each of the middle layer pairs is smaller than a thickness of the second layer of each of the middle layer pairs. A refractive index of the first layer is greater than a refractive index of the second layer.

Micro LED display device

A protection layer for use in fabrication of failure analysis (FA) sample is disclosed, which principally comprises a first thin film, a buffer thin film and a second thin film By forming the protection layer on a surface of a malfunction device die, a FA sample of the malfunction device die is obtained. As a result, in the case of treating the sample with a FIB thinning process, there are no cracks, distortion, and/or collapse resulted from inter-elemental isobaric interferences, stress effect or charge accumulation occurring on the surface layer of the malfunction device die because of the protection of the protection layer. On the other hand, this protection layer can also be applied to a microLED element or a VCSEL element, so as to make microLED element and the VCSEL element possess excellent stress withstanding capability.

Protection layer and method for making the same

A method of making a semiconductor device includes:

Method of making a semiconductor device

A lighting device includes a plurality of light-emitting diodes including a first light-emitting diode with a non-rectangular shape in a top view, a submount to which each of the plurality of light-emitting diodes is coupled, and a plurality of conductive elements formed between the submount and the plurality of light-emitting diodes to electrically connecting at least a portion of the plurality of light-emitting diodes with each other in series.

Lighting device

A deep UV LED chip includes a light-emitting unit, an electrode unit, an electron blocking layer, and an optical layer. The electron blocking layer is disposed between a multiple quantum well layer and a p-type aluminum gallium nitride layer of the light-emitting unit. The optical layer is formed on the light-emitting unit and has a refractive index ranging from 1.0 to 2.3. Another deep UV LED chip further includes a light-transmitting substrate. The optical layer is formed on the light-transmitting substrate and has a refractive index ranging from 1.0 to a refractive index of the light-transmitting substrate. A package structure containing the deep UV LED chip is also disclosed.

Deep ultraviolet light-emitting diode chip and package structure containing the same

An optical sheet is disclosed in the present invention and comprises a substrate, a reflective layer and a plurality of pixels. The reflective layer is disposed on the substrate. The pixels are composed of several quantum dot fluorescent powders respectively and arrayed on the reflective layer. In addition, a method for manufacturing the above optical sheet, a light emitting diodes module and a display using the above optical sheet are also disclosed in the present invention.

Optical sheet, method for manufacturing the same, light emitting diodes module and display using the same

The present disclosure involves a method of fabricating a semiconductor device. A surface of a silicon wafer is cleaned. A first buffer layer is then epitaxially grown on the silicon wafer. The first buffer layer contains an aluminum nitride (AlN) material. A second buffer layer is then epitaxially grown on the first buffer layer. The second buffer layer includes a plurality of aluminum gallium nitride (AlGaN) sub-layers. Each of the sub-layers has a respective value for x that is between 0 and 1. A value of x for each sub-layer is a function of its position within the second buffer layer. A first gallium nitride (GaN) layer is epitaxially grown over the second buffer layer. A third buffer layer is then epitaxially grown over the first GaN layer. A second GaN layer is then epitaxially grown over the third buffer layer.

Method of growing a high quality III-V compound layer on a silicon substrate

A light emitting device is provided. The light emitting device includes a substrate, an N type semiconductor layer formed on the substrate, an active layer, an electron-blocking layer, and a P type semiconductor layer formed on the electron-blocking layer. An N side electrode is formed on a first portion of the N type semiconductor layer, and the active layer is formed on a second portion of the N type semiconductor layer. The electron-blocking layer is a super lattice multi-layer structure formed on the active layer, the P type semiconductor layer is formed on the electron-blocking layer, and a P side electrode is formed on a portion of the P type semiconductor layer.

Semiconductor light emitting device

A high electron mobility transistor is provided, which includes a substrate, a superlattice structure formed on the substrate, and a transistor epitaxial structure formed on the superlattice structure such that the superlattice structure is interposed between the substrate and the transistor epitaxial layer. As the high electron mobility transistor has the carbon-doped AlN/GaN superlattice structure between the substrate and the transistor epitaxial layer. Thus, the present invention can effectively reduce vertical leakage current, so as to improve the epitaxial quality and the breakdown voltage of the high electron mobility transistor.

High electron mobility transistor

The present disclosure involves an apparatus. The apparatus includes a photonic die structure that includes a light-emitting diode (LED) die. The LED die is a vertical LED die in some embodiments. The LED die includes a substrate. A p-doped III-V compound layer and an n-doped III-V compound layer are each disposed over the substrate. A multiple quantum well (MQW) layer is disposed between the p-doped III-V compound layer and the n-doped III-V compound layer. The p-doped III-V compound layer includes a first region having a non-exponential doping concentration characteristic and a second region having an exponential doping concentration characteristic. In some embodiments, the second region is formed using a lower pressure than the first region.

Growing an improved P-GaN layer of an LED through pressure ramping

A light emitting diode device is provided, which comprises a silicon-based substrate, a buffer layer, a super lattice structure layer, a nano-structure layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The buffer layer is formed on the silicon-based substrate, the super lattice structure layer is formed on the buffer layer, the nano-structure layer is formed on the super lattice structure layer, a first semiconductor layer is formed on the nano-structure layer, and the light emitting layer is formed between the first semiconductor layer and the second semiconductor layer. The super lattice layer and the nano-structure can release the stress within the light emitting diode device, and reduce the epitaxy defect, so that the internal quantum effect and the external quantum effect can be increased.

Light emitting diode device having super lattice structure and a nano-structure layer

The present disclosure involves an illumination apparatus. The illumination apparatus includes an n-doped semiconductor compound layer, a p-doped semiconductor compound layer spaced apart from the n-doped semiconductor compound layer, and a multiple-quantum-well (MQW) disposed between the first semiconductor compound layer and the second semiconductor compound layer. The MQW includes a plurality of alternating first and second layers. The first layers of the MQW have substantially uniform thicknesses. The second layers have graded thicknesses with respect to distances from the p-doped semiconductor compound layer. A subset of the second layers located most adjacent to the p-doped semiconductor compound layer is doped with a p-type dopant. The doped second layers have graded doping concentration levels that vary with respect to distances from the p-doped semiconductor layer.

III-V group compound devices with improved efficiency and droop rate

A lighting apparatus includes a polygon die including a plurality of light-emitting diodes (LEDs), and a submount to which each of the LEDs is coupled. Each LED includes a plurality of epi-layers which contains a p-type layer, an n-type layer, and a multiple quantum well (MQW) disposed between the p-type layer and the n-type layer, and a p-type electrode and an n-type electrode which are electrically coupled to the p-type layer and the n-type layer, respectively. The p-type and the n-type electrodes are located between the submount and the epi-layers. The submount contains a plurality of conductive elements configured to electrically couple at least a portion of the plurality of LEDs in series. At least some of the plurality of LEDs have non-rectangular top view shapes.

High voltage LED with improved heat dissipation and light extraction

The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150&#xb0; C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit.

Method for fabricating power-generating module with solar cell

Growing community of inventors

Hsinchu, Taiwan

Hao-Chung Kuo