Advanced Micro Devices Corporation

Samsung Electronics Co., Ltd.

Ati Technologies Ulc

Hanwoo Cho

Gerald Robert Talbot

Brian W Amick

Richard W Reeves

Shawn Searles

Michael J Tresidder

Milam Paraschou

Jeffrey Cooper

Damon Tohidi

Thomas H Likens, Iii

Chad S Gallun

Varun Gupta

Gurunath Dollin

Eric Ian Carpenter

Scott F Dow

Guhan Krishnan

Nicholas Humphries

Ronald L Pettyjohn

Eric Rowe

Jonathan Mercer Owen

Philip Enrique Madrid

Tahsin Askar

Jelena Ilic

Ryan J Hensley

Nicholas T Humphries

Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Deskewing method for a physical layer interface on a multi-chip module

A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

Dynamic RAM Phy interface with configurable power states

A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register.

Method and apparatus to reduce memory read latency

A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

Memory diagnostics system and method with hardware-based read/write patterns

A data processing device is configured so that, in a test mode of operation, the phase of an output signal of a second programmable delay module (PDM) is based on the phase of the input signal of the first PDM. To test the first and second PDMs, the output signal of the first PDM is set to each of a first set of phases and the corresponding phase of the output signal of the second PDM is compared to determine whether the performance of the first and second PDMs match a specification. Accordingly, the first and second PDMs are qualified based on their relative performance, reducing the need for test structures that consume an undesirably large amount of area.

Programmable delay module testing device and methods thereof

A method is provided for utilizing four error correcting code (ECC) pin connections of a PCI/PCI-X bus for one of Grant (GNT) and Request (REQ) pin connections. The method determines a mode of the PCI bus to be PCI-X Mode 1, PCI-X Mode 2, or PCI. If the determined mode is PCI-X Mode 2, the four ECC pin connections are used as ECC pin connections, and if the determined mode is PCI or PCI-X Mode 1, each of the four ECC pin connections is used as a GNT pin connection or a REQ pin connection.

PCI-X error correcting code (ECC) pin sharing configuration

A method is provided for selectively using a PCIXCAP pin input to detect PCI/PCI-X bus mode or as DC pin input. The method provides a PCI/PCI-X device having PCIXCAP pin input, and a circuit having a plurality of voltage level detection structures and an output corresponding to each voltage level detection structure. Each output is received by a first logic to detect the PCI bus mode of a device defining a first, PCIXCAP mode for the pin input. The method ensures that one of the plurality of voltage level detection structures may be used as a DC signal logic to provide a DC output signal to a second logic. A mode of the PCIXCAP pin input is selected so as to provide the DC output signal under conditions where the PCI/PCI-X bus mode is not being detected. In an embodiment, the DC output signal is used in as a PCI Hot-Plug interface signal.

PCIXCAP pin input sharing configuration for additional use as PCI hot plug interface pin input

In a microprocessor module assembly, voltage regulators are integrated into the module and adapted for use with a processor and support electronics likewise mounted on the module. The voltage regulators receive a fixed imput voltage from a motherboard interface and provide modified regulated output voltages to the processor and support electronics. In this manner, the processor module is readily upgradable such that future generations are compatible with a fixed motherboard interface without the need for upgrading voltage regulators on the motherboard. In a preferred embodiment, bulk decoupling capacitance is provided on the processor assembly to stabilize the DC output voltage of the voltage regulators.

Microprocessor module with integrated voltage regulators

In a common processor module/motherboard interface, an interface protocol is defined such that a replacement processor module can be recognized by a common motherboard and such that a common processor module can be compatible with multiple motherboards. A module information field stored on a processor module includes status information pertaining to the processor module. When the processor module is coupled to a motherboard, the motherboard downloads the module information field and generates initialization commands for the processor module based on the retrieved module information field. The commands are transferred to the processor module for initialization of the processor.

Dynamic initialization of processor module via motherboard interface

A common motherboard interface accommodates processor modules of different processor architectures. The system comprises an interface for communicating with a processor module inserted at the motherboard. The interface receives an identifier signal from the processor module. The identifier signal identifies the processor module architecture. An architecture selection circuit selectively exchanges processor architecture specific signals with the processor module based on the identifier signal. In this manner, a multiple of processor modules of completely different processor architectures can share a common motherboard, thereby providing a system that can be field-upgraded by processor modules of different architectures, or simply allowing the same motherboard to be employed in two different products of different processor architectures.

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Acton, MA, United States of America

Hanwoo Cho