Zilog, Inc.

Cirrus Logic Inc.

Centillium Communications, Inc.

Hanumanthrao Nimishakavi

Ravi Swami

Craig A MacKenna

Niraj Kumar

Joseph G DeCarolis

Chung Liang

Ikuji Nobugaki

Ravi Narayanaswami

To enhance the upstream data traffic management in an EPON, a scheme is employed to allocate transmission windows for upstream data transmitted from the subscribers' ONUs to an OLT. The queues of a logical link are grouped into queue containers, and the OLT allocates upstream transmission windows to the queue containers. Logical links assigns the upstream transmission window allocated to a queue container to the queues in the queue containers.

Enhanced upstream data traffic management for EPON

A communication interface unit (128) facilitates data word exchanges between a parallel driven bus (210) and a serial driven communication channel (136) by performing both parallel-to-serial and serial-to-parallel data conversion functions. A transmitter circuit (200) is included in the communication interface unit (128), which performs parallel-to-serial data conversion employing a multiplexer circuit (204) and control logic circuitry (208). The multiplexer circuit (204) concurrently receives a plurality of data bits of a data word being transferred, and the control logic circuitry (208) thereupon causes the plurality of data bits of the data word to be successively passed through the multiplexer circuit (204) so as to perform parallel-to-serial conversion. A receiver circuit (300) may also be included in the communication interface unit (128), which performs serial-to-parallel data conversion employing a plurality of flip-flops (304) and control logic circuitry (308). The plurality of flip-flops (304) each receive a plurality of data bits of a data word being transferred, and the control logic circuitry (308) thereupon causes the plurality of data bits of the data word to be successively latched into the plurality of flip-flops (304) so as to perform serial-to-parallel conversion.

Communication interface unit employing two multiplexer circuits and

A time multiplexing technique and corresponding circuitry is described which provides controlled access to one processor at a time of two or more access requesting processors, to a system resource shared by the two or more processors. Each of the access requesting processors is connected to an input of a plurality of multiplexers. Each of the multiplexers has a select input which determines which of the multiplexer's inputs becomes its output which is in turn, connected to an appropriate input of the system resource. By connecting together the select inputs of the multiplexers, access to the shared system resource is alternated between the two or more processors by alternating the value of the select input in response to the system clock.

Technique and circuit for providing two or more processors with time

A digital phase-locked loop for receiving an encoded stream of data and generating a receive clock signal therefrom is provided with a counter, such as a down counter, having an adjustable start count value. An edge detector detects the rising and falling edges within a stream of data. The detection of an edge causes the counter to start counting from the start count value towards a terminal value. A receive clock generator is provided that generates a receive clock signal, the receive clock generator being responsive to the counter reaching at least a first predetermined value to change a level of the receive clock signal. The use of a down counter that is loaded with a start count value upon the detection of an edge provides fast re-synchronization when an edge has been missed, while providing accurate recovery of the clock from the encoded stream of data.

Fast synchronizing digital phase-locked loop for recovering clock

A time multiplexing technique and corresponding circuitry which provides controlled access to one processor at a time of two or more access requesting processors, to a system resource shared by the two or more processors. Each of the access requesting processors is connected to an input of a plurality of multiplexers. Each of the multiplexers has a select input which determines which of the multiplexer's inputs becomes its output which is in turn, connected to an appropriate input of the system resource. By connecting together the select inputs of the multiplexers, access to the shared system resource is alternated between the two or more processors by alternating the value of the select input in response to the system clock.

A mode control circuit is disclosed which generates a mode control signal in response to an illegal state detected as a combination of inputs and outputs. An illegal state is forced by the application of a fixed voltage to an output pin. The mode control signal is used to switch input-output signals of a megacell internal to an application specific integrated circuit to the output pins of the package so that testing of the megacell is facilitated.

Circuit for generating a mode control signal

A bidirectional interrupt technique and mechanism is described for handling programmable length interrupt messages between two devices, preferably both processors, through dual, programmably defined memory queues. The technique and mechanism automatically updates a read and write address counter, a queue count register, and an interrupt count register for each direction of the flow of interrupts.

Queued interrupt mechanism with supplementary command/status/message

A semiconductor multi-device system incorporated on a single semiconductor chip is disclosed including a central processing unit, a bus, a plurality of peripherals, a plurality of on-chip data bus drivers connected to selected lines of the bus, and logic means for controlling the operation of the on-chip data bus drivers. The multi-device system of the invention is capable of interacting with off-chip components including an off-chip processing unit and off-chip peripherals. The off-chip components may also include a plurality of off-chip data bus drivers that drive data signals onto and off of an off-chip data bus. The on-chip and off-chip drivers must cooperate in order for data signals to transfer properly between the on-chip and off-chip components. The logic means of the invention is designed so as to minimize the logic necessary to cause the on-chip drivers and the off-chip drivers to cooperate properly. The logic means of the invention is also designed to function properly regardless of whether the on-chip processing unit or the off-chip processing unit is in control of the overall system comprising both on-chip and off-chip components. The logic means is also designed to control the operation of the on-chip drivers in a simple and efficient manner. Thus, a multi-device system is disclosed which is a significant improvement over those of the prior art.

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Fremont, CA, United States of America

Hanumanthrao Nimishakavi