Samsung Electronics Co., Ltd.

Hansol Seok

Gihwan Kim

Jongheun Lim

Changsun Hwang

Boun Yoon

Byoungho Kwon

Dongseog Eun

Chungki Min

Kichul Park

Ki-Woong Kim

Youngjin Kwon

An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.

Integrated circuit device including vertical memory device

Semiconductor devices and methods of forming the same are provided. The methods may include forming a stacked structure that may include a stacking area and a stepped area and may include first layers and second layers alternately stacked. The second layers may have a stepped shape in the stepped area, and the stepped area may include at least one flat area and at least one inclined stepped area. The methods may also include forming a capping insulating layer covering the stacked structure. The capping insulating layer may include a first capping region having a first upper surface and a second capping region having a second upper surface at a lower level than the first upper surface. The methods may further include patterning the capping insulating layer to form protrusions at least one of which overlaps the stepped area and then planarizing the capping insulating layer.

Planarization method of a capping insulating layer, a method of forming a semiconductor device using the same, and a semiconductor device formed thereby

A semiconductor memory device may include a selection transistor on a semiconductor substrate, an interlayered insulating layer covering the selection transistor, a lower contact plug coupled to a drain region of the selection transistor and configured to penetrate the interlayered insulating layer, and a magnetic tunnel junction pattern coupled to the lower contact plug. The lower contact plug may include a metal pattern and a capping metal pattern in contact with a top surface of the metal pattern. The capping metal pattern may include a top surface having a surface roughness that is smaller than a surface roughness of the top surface of the metal pattern. The magnetic tunnel junction pattern may include bottom and top electrodes, a lower magnetic layer and an upper magnetic layer between the top and bottom electrodes, and a tunnel barrier layer between the lower magnetic layer and the upper magnetic layer.

Semiconductor memory devices

Growing community of inventors

Suwon-si, South Korea

Hansol Seok