Silicon Graphics, Incorporated

Synopsys, Inc.

Tricn Inc.

Hansel A Collins

David M Parry

Paul Everhardt

John Eric Linstadt

David P Chengson

Edward C Priest

Greg Chesson

Scott W Alvarez

A delay line includes a delay chain consisting of series-connected NAND gate delay stages with a delayed output signal extracted from the final delay stage. Tap decode gates are preferably used to 'inject' the input signal to be delayed into the delay chain using one input of the NAND gate delay stage, referred to as an 'injection point.' The desired delay is achieved by selecting an injection point relative to the final delay stage, or exit point, of the delay chain. Selection of an injection point is provided by the binary decode of a tap address that activates the injection NAND gate delay stage, allowing the injected signal to propagate from the activated injection point to the exit point of the delay chain.

Multiple-input, single-exit delay line architecture

A system performs a two-step skew compensation procedure by first correcting for any phase error alignment between a parallel link clock and data signal edges of each data channel, thereby allowing the received data bits to be correctly sampled. Then, a second step is performed to 'word-align' the bits into the original format, which is accomplished with a Skew Synchronizing Marker (SSM) byte in a data FIFO of each data channel. The SSM byte is transmitted on each data channel and terminates the skew compensation procedure. When the SSM byte is detected by logic in the data FIFO of each data channel, the data FIFO employs the SSM byte to initialize the read and write pointers to properly align the output data.

Relative dynamic skew compensation of parallel data lines

A clock edge placement circuit for implementing source synchronous communication between integrated circuit devices. The clock edge placement circuit includes a delay line having an input to receive a clock signal from an external clock source. A corresponding output is included to provide the clock signal to external logic elements. The delay line structure adapted to add a propagation delay to the input, wherein the propagation delay is sized such that the phase of the clock signal is adjusted to control synchronous sampling by the external logic elements. The delay line is adapted to dynamically adjust the delay such that the phase of the clock signal at the output remains adjusted to control synchronous sampling by the external logic as variables affecting the phase of the clock signal change over time. A series of taps are included within the delay line. The delay line uses the series of taps to add a variable delay for adjusting the phase of the clock signal. Each tap is configured to add an incremental delay to the input to generate the variable delay.

Method and system for clock cycle measurement and delay offset

The present invention comprises a dynamic skew compensation circuit. The present invention includes a receiver, a plurality of channel inputs built into the receiver, and a delay stack structure coupled to the plurality of channel inputs. The receiver is adapted to accept data from a parallel data transfer cable. The channel inputs couple to each of the individual communications channels which comprise the parallel data transfer cable. The delay stack structure includes a plurality of delay stacks, each coupled to a respective channel input. Each delay stack dynamically selects an additional delay amount for its respective communications channel such that each communications channel of the parallel data transfer cable is deskewed with respect to the others. In so doing, the distances across which data can be received and the speeds at which data is transferred via the parallel data transfer cable is increased.

Method and system for deskewing parallel bus channels

The present invention incorporates a variable delay circuit to add delay to a clock signal. In a preferred embodiment of the present invention, the delay is determined and fixed by a circuit employing the concept of a lock-and-leave circuit. This has the effect of fine tuning the delay determined by the lock-and-leave circuit. Mode bits allow a user to control the rate at which fine tuning occurs. Three update rates are provided in a preferred embodiment of the present invention. They are slow, medium, and fast.

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Mountain View, CA, United States of America

Hansel A Collins