Digital Equipment Corporation

Other

Hansel A Collins

Richard B Watson, Jr

Russell Iknaian

David W Hartwell

Michael B Evans

Michael A Gagliardo

James E Tessari

John J Lynch

Kumar Chinnaswamy

Timothy P Fissette

Donald W Smelser

Donald C Pierce

David T Mayo

Robert Norman Crouse

Noreen Hession

Edward H Utzig

A memory system for a digital computer has first and second memory modules having differing numbers of independently-accessible banks and unlike capacities. The digital computer also has an addressing arrangement that employs horizontal stacking for interleaving together the banks of both the first and second memory modules, such that the first memory module is interleaved to a first level and the second memory module to a second, different level. The invention also embraces a method of interleaving the memory system employing horizontal stacking. In usual applications, horizontal stacking permits the memory system to be interleaved to a higher level than that achieved by conventional vertical stacking schemes.

System for interleaving memory modules and banks

A DC-to-DC voltage convertor is made up of a capacitor array having plural capacitor elements (C.sub.p1, C.sub.p2, C.sub.p3) and a plurality of switches (S2 . . . S10) which are switchable between at least two states. When the switches are switched in the first state, the capacitor elements are connected in series, and when the switches are connected in the second state, the capacitor elements are connected in parallel. The DC-to-DC voltage convertor may be configured as a step-down convertor (FIG. 2a) or a step-up convertor (FIG. 2b).

High power switched capacitor voltage conversion and regulation apparatus

A memory management and arbitration technique that reduces system bus contention by eliminating memory bank conflicts employs a restrictive, distributive memory-arbitration scheme, and an improved address decoder for decoding addresses of software reconfigurable memory. In the memory-arbitration scheme, each commander node desiring access to a particular memory bank first determines whether that memory bank is 'available' before initiating access to that memory bank, with the determination being made before requesting control of the system bus. A memory bank is 'available' if it was not accessed during a predetermined number (e.g., two) of the immediately previously-occurring arbitrations for the system bus. The address decoder includes a mapping register that stores information concerning the addresses assigned to, and the structure of, the memory module. The address decoder also has an address/range decoder section, an interleaved decoder section, and a bank decoder section. The address/range and interleave decoder sections determine the memory module containing the address being decoded. This can be combined with the output of the bank decoder section to identify the particular memory bank on the system bus that contains the address.

Memory bank management and arbitration in multiprocessor computer system

A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a clock repeater chip, a module transmission network and a clock distribution network of an integrated circuit (IC) chip associated with a clock repeater chip. Circuits of the remote delay regulator are contained on the repeater chip and on the associated IC chip. Delay measurement of the remote IC clock distribution network is provided by sensing the clock signal at the beginning of the network using a BEFORE sense tap and at the end of the network using an AFTER sense tap. The BEFORE and AFTER sense taps are routed to a signal generation circuit on the repeater chip where measurement signals are generated that define the beginning and end of a measurement cycle. A clock delay path circuit on the repeater chip contains the logic circuitry required to measure and compensate for the intrinsic propagation delays of the repeater chip, the transmission network and the IC chip. The logic circuitry includes a measurement latch circuit and a measurement delay line having tapped outputs coupled to the latch circuit.

Method and apparatus for clock skew reduction through remote delay

Methods and apparatus for immunizing dynamic random access memory (DRAM) modules in the data processing system against data loss from transitions that occur with memory mode switching during the scan operation and permitting normal operations to be performed on the memory modules regardless of the state of the system clocks.

Method and apparatus for performing diagnosis scanning of a memory unit

An 'absolute' delay regulator of a clock repeater chip performs a precise measurement of the propagation delay of a clock signal and adjusts that delay so as to maintain a fixed-phase relationship with an input clock signal. A replica loop accurately replicates the internal path and external loading, including input and output buffers, of the chip. The output of the replica loop drives a delay line whose tapped outputs provide an absolute delay measurement. Results of the measurement are decoded and used to select an appropriate tap to another delay line used to insert a desired amount of delay to an output clock signal.

Method and apparatus for clock skew reduction through absolute delay

Mode switching for a memory system with diagnostic scan

A method and apparatus for testing each memory location of a memory device, the method comprising the steps of: generating each of the memory addresses corresponding to each memory location in a pseudo-random order; generating a pseudo-random series of data words; storing one of the data words at each memory location; reading each data word back from memory; regenerating the series of data words; and comparing each read data word to the corresponding regenerated data word. The invention features generating and storing a second series of data words, each data word being inverse of the data words in the first series. The second series of data words are read from memory and compared to regenerated data. The invention also features a novel linear feedback shift register for generating the pseudo-random memory addresses and can generate the address zero. An accumulating register is utilized to store the approximate location of malfunctioning memory locations.

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Clinton, MA, United States of America

Hansel A Collins