Nvidia Corporation

Hans Wolfgang Schulze

Barry A Wagner

Russell R Newcomb

David Haley

Ludger Mimberg

Samuel Richard Duell

Qi Lin

Ryan Speiser

Chad Plummer

Erik Zuroski

Darryl Moore

James Van Veghel

The disclosure provides a cooling solution that evaluates the thermal environment of a computer component based on transient thermal responses of the computer component. The transient thermal responses are generated by measuring the temperature rise of the computer component over a designated amount of time for multiple 'good' assemblies and multiple “bad” assemblies to determine a duration and allowable temperature rise needed to set a pass/fail criteria for different failure modes of cooling devices. A cooling device may not be operating as designed due to damage, needed maintenance, missing thermal interface material (TIM), improper installation, etc. From the transient thermal responses, a thermal problem, such as a malfunctioning fan, can be determined and a corrective action can be performed.

Thermal environment evaluation and compensation for computer components

A fan control module configured to control the speed of a fan receives a signal that indicates the power used by a graphics processing unit (GPU) and a signal that indicates the GPU temperature. Whenever the GPU power exceeds a power threshold level, but the GPU temperature is below a temperature threshold level, the control module turns the fan on and causes the fan to operate at a minimum speed. Whenever the GPU temperature is above the temperature threshold, the control module causes the fan speed to increase with increasing temperature, regardless of power. The control module turns the fan off only when both the GPU temperature is below the temperature threshold and the GPU power is below the power threshold. Although the algorithm is discussed in conjunction with a GPU, the algorithm can be implemented with any type of processor or subsystem that needs to be fan-cooled.

Techniques for reducing fan cycling

Techniques for selecting a boot display device in the multi-GPU configured computing device include a graphic initialization routine for determining a topology of a plurality of GPUs. It is then determined if a display is coupled to any of the plurality of GPUs. The determination of whether the display is coupled to a GPU is communicated to the other of the plurality of GPUs based upon the determined topology. Thereafter, selection of a given GPU as a primary boot device, by a system initialization routine, is influenced by representing each GPU not coupled to the display as a graphics device and the GPUs coupled to a given display as the primary boot device if one or more displays are coupled to GPUs, and by representing the given GPU as the primary boot device and all other GPUs as graphics devices when the display is not coupled to any of the GPUs. In addition or in the alternative selection of the given GPU as the primary boot device may be influenced by hiding the expansion ROM of GPUs not coupled to a display.

Boot display device detection and selection techniques in multi-GPU devices

A synchronous memory device is configured to switch into and out of a full speed mode to change speed the speed of data transactions without significantly disturbing the frequency of a clock input to a PLL or DLL that provides the internal clock for the synchronous memory device. Since the PLL or DLL receives a clock signal whether or not the synchronous memory device is in a non-full speed mode, the PLL or DLL does not need to settle or relock when the clock signal is reapplied to exit a different speed mode and return to the full speed mode. Therefore, the latency incurred to switch into and out of different speed modes is reduced by eliminating or substantially reducing the time for settling or relocking the PLL or DLL.

Low latency synchronous memory performance switching

Low latency synchronous memory performance switching with drift refresh

Low latency synchronous memory performance switching using update control

A regulator set point circuit. The circuit includes a voltage regulator configured to produce an output voltage. An adjustable voltage source is coupled to the voltage regulator via a feedback circuit, and is configured to generate a voltage adjust signal to control the output voltage.

Power supply dynamic set point circuit

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Sunnyvale, CA, United States of America

Hans Wolfgang Schulze