Infineon Technologies Austria Ag

Infineon Technologies Ag

Infineon Technologies Dresden Gmbh

Infineon Technologies Dresden Gmbh & Co . Kg

Hans Weber

Franz Hirler

Hans-Joachim Schulze

Daniel Tutuc

Armin Willmeroth

Anton Mauder

Gerald Deboy

Christian Fachmann

Andreas Riegler

Andreas Voerckel

Stefan Gamerith

Gabor Mezoesi

Werner Schustereder

Michael Treu

Ingo Muri

Matteo-Alessandro Kutschak

Roman Knoefler

Maximilian Treiber

Dirk Ahlers

Markus Schmitt

Wolfgang Jantscher

Markus Zundel

Andreas Peter Meiser

Johannes Georg Laven

Rolf Weis

Johannes Baumgartl

Winfried Kaindl

Andreas Moser

Roland Rupp

Helmut Strack

Uwe Wahl

Stefan Sedlmaier

Jens-Peer Stengl

Manfred Pippan

Kurt Sorschag

Jenoe Tihanyi

Oliver Haeberlen

Matthias Stecher

Peter Irsigler

Joachim Weyers

Klemens Pruegl

Matthias Kuenle

Björn Fischer

Lincoln O'Riain

Markus Rochel

Thomas Wahls

Birgit Von Ehrenwall

Ralf Erichsen

Frank Dieter Pfirsch

Martin Poelzl

Walter Rieger

Carsten Von Koblinski

Armin Tilke

Martin Henning Vielemeyer

Moriz Jelinek

Herbert Schäfer

Bjoern Fischer

David Kammerlander

Martin Pölzl

Gerhard Nöbauer

Jenö Tihanyi

Helmut Gassel

Michael Rüb

Thomas Rupp

Martin M&auml;rz

Martin März

Felix Schubert

Miguel Cuadron Marion

Gerhard Silvester Neugschwandtner

A transistor device is disclosed. The transistor device includes: a semiconductor body (); a drift region () in the semiconductor body (); a plurality of transistor cells (); and a gate node (G) and a source node (S), wherein each of the plurality of transistor cells () includes: a first trench electrode () insulated from the semiconductor body () by a first dielectric layer (); a second trench electrode () insulated from the semiconductor body () by a second dielectric layer (); a source region () and a body region () in a first mesa region () between the first trench electrode () and the second trench electrode (); and a compensation region (), wherein the compensation region () adjoins the body region (), the first dielectric (), the second dielectric (), and forms a pn-junction with the drift region (), and wherein from the first trench electrode () and the second trench electrode () at least the first trench electrode () is connected to the gate node (G).

Superjunction transistor device

Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

Method for producing a superjunction device

A semiconductor device is proposed. An example of the semiconductor device includes a semiconductor body having a first main surface. A trench structure extends into the semiconductor body from the first main surface. The trench structure includes a trench electrode structure and a trench dielectric structure. The trench dielectric structure includes a gate dielectric in an upper part of the trench dielectric structure and a gap in a lower part of the trench dielectric structure. The semiconductor device further includes a body region adjoining the gate dielectric at a sidewall of the trench structure in the upper part of the trench dielectric structure. The gate dielectric extends deeper into the semiconductor body along the sidewall than the body region.

Semiconductor device including a trench structure having a trench dielectric structure with a gap

An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device () and a second transistor device (); a first biasing circuit () connected in parallel with a load path of the first transistor device () and comprising a first electronic switch (); a second biasing circuit () connected in parallel with a load path of the second transistor device () and comprising a second electronic switch (); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device () and the second electronic switch () based on the first half-bridge input signal (Sin), and drive the second transistor device () and the first electronic switch () based on the second half-bridge input signal (Sina).

Electronic circuit with a transistor device and a biasing circuit

A method for forming a drift region of a superjunction transistor and a superjunction transistor device are disclosed. The method includes forming first regions of a first doping type and second regions of a second type in a semiconductor body such that the first and second regions are arranged alternatingly in the body. The first and second regions are formed by: forming trenches in at least one semiconductor layer; implanting first type dopant atoms and second type dopant atoms into opposing sidewalls of the trenches; filling the trenches with a semiconductor material; and diffusing the dopant atoms in a thermal process so that the first type dopant atoms form the first regions and the second type dopant atoms form the second regions. Each trench has a first width, the trenches are separated by mesa regions each having a second width, and the first width is greater than the second width.

Superjunction transistor device and method for forming a superjunction transistor device

A method and a transistor device are disclosed. The transistor device includes: a semiconductor body; first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of the semiconductor body; transistor cells in the inner region of the semiconductor body, each transistor cell including a body region and a source region, the transistor cells including a common drain region; and a buffer region arranged between the drain region and the first and second regions. A dopant dose in the first and second regions decreases towards an edge surface of the semiconductor body. A dopant dose in the buffer region decreases towards the edge surface.

A method includes forming a trench in a first surface in an edge region of a semiconductor body, forming a plurality of superjunction transistor cells in an inner region of a semiconductor body, and forming an insulation layer on the first surface of the semiconductor body in the edge region and in the inner region, wherein forming the insulation layer includes a thermal oxidation process.

Method for forming an insulation layer in a semiconductor body and transistor device

Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.

Electronic circuit having a transistor device and a biasing circuit

A method for producing a semiconductor device includes forming transistor cells in a semiconductor body, each cell including a drift region separated from a source region by a body region, a gate electrode dielectrically insulated from the body region, and a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in a vertical direction. Forming the drift and compensation regions includes performing a first implantation step, thereby implanting first and second type dopant atoms into the semiconductor body, wherein an implantation dose of at least one of the first type dopant atoms and the second type dopant atoms for each of at least two sections of the semiconductor body differs from the implantation dose of the corresponding type of dopant atoms of at least one other section of the at least two sections.

A connection body which comprises a base structure at least predominantly made of a semiconductor oxide material or glass material, and an electrically conductive wiring structure on and/or in the base structure, wherein the electrically conductive wiring structure comprises at least one vertical wiring section with a first lateral dimension on and/or in the base structure and at least one lateral wiring section connected with the at least one vertical wiring section, wherein the at least one lateral wiring section has a second lateral dimension on and/or in the base structure, which is different to the first lateral dimension.

Semiconductor oxide or glass based connection body with wiring structure

A semiconductor device includes a semiconductor body having a first surface and second surface opposite to the first surface in a vertical direction, and a plurality of transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes at least two source regions, first and second gate electrodes spaced apart from each other in a first horizontal direction and arranged adjacent to and dielectrically insulated from a continuous body region, a drift region separated from the at least two source regions by the body region, and at least three contact plugs extending from the body region towards a source electrode in the vertical direction. The at least three contact plugs are arranged successively between the first and second gate electrodes. Only the two outermost contact plugs that are arranged closest to the first and second gate electrodes, respectively, directly adjoin at least one of the source regions.

Semiconductor device

A transistor device and a method for forming a transistor device are disclosed. The method includes: forming first regions of a first doping type and second regions of a second doping type in inner and edge regions of a semiconductor body; and forming body and source regions of transistor cells in the inner region. Forming the first and second regions includes: forming first and second implanted regions in the inner and edge regions, each first implanted region including at least dopant atoms of a first doping type and each second implanted region including at least dopant atoms of a second doping type; and diffusing the dopant atoms of both doping types in a thermal process such that dopant atoms of at least one of the first and second doping types have at least one of different diffusion rates and diffusion lengths in the inner and edge regions.

Method for forming a superjunction transistor device

Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.

In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.

Method of manufacturing a superjunction semiconductor device

Growing community of inventors

Bayerisch Gmain, Germany

Hans Weber