Lattice Semiconductor Corporation

Imp Inc.

Minnesota Mining and Manufacturing Company

National Acquisition Sub, Inc.

Hans W Klein

Jian Li

Om P Agrawal

Paul Hildebrant

Sriram Narayan

Harald Weller

Frederic N F Deboes

Geoffrey R Rickard

Bal S Sandhu

Ludmil Nikolov

Robert M Bartel

Srirama Chandra

Corey D Petersen

Yaohua Yang

Douglas C Morse

Joey I Doernberg

Geoffrey R Richard

Moises E Robinson

Ching Wang

Paul R Dougherty

An acoustic processing module receives an acoustic signal, and outputs an analog output signal. Microphone sensors are provided for generating a corresponding electrical signal in response to the acoustic signal. A signal processing circuit is connected to the microphone sensors, and processes the electrical signals according to one or more analog signal processing functions to generate the analog output signal. An integrated casing encapsulates the microphone sensors and the analog processing circuit, and prevents external interference from affecting any electrical signals within the integrated casing.

Small-footprint microphone module with signal processing functionality

Power-sequencing controllers are connected to allow more complex power sequencing and/or larger numbers of voltage supplies to be monitored than with a single controller. Power-on-reset (POR) output signals from the 'slave' controllers are connected by a wired-OR, and the composite output is used as a reset signal or indicator signal by the 'master' controller. An output from the master controller coupled to the composite input signal is connected with the {overscore (POR)} output of the master controller by a wired-OR, and this composite signal is coupled to the reset terminals of the slave controllers. Connecting controllers in a master/slave configuration allows prevents any of the slave devices from starting until all the devices have been released, resulting in synchronous processing of subsequent signals and events.

Expansion method for complex power-sequencing applications

Systems and methods are disclosed to provide clock generation. In accordance with one embodiment, a clock generator chip is provided that is configurable and in-system programmable and includes a flexible skew control architecture. The clock generator chip may also provide programmable input circuits, programmable output circuits, and permit a JTAG boundary scan.

Clock generator with skew control

Systems and methods are disclosed to provide clock generation. In accordance with one embodiment, a clock generator chip is provided that is configurable and in-system programmable. The clock generator chip may provide programmable input circuits, programmable output circuits, and permit a JTAG boundary scan.

Clock generator

Device driver circuits based on H-bridges can be implemented to provide linear control of the H-bridge, reduce power losses, and reduce certain component size/cost. The driver circuits can use two feedback loops to operate the H-bridge in different regions and to guarantee that current flows through an H-bridge load device, such as a thermoelectric cooler, in only one direction at a given time. The H-bridge driver circuits can remove the possibility of high currents bypassing the load device and thus going directly through the switches on either side of the H-bridge driver. The H-bridge driver circuits also ensure careful control of the current applied to the H-bridge load device. Such driver circuits are particularly useful for controlling the current applied to thermoelectric devices.

Linear thermoelectric device driver

A programming technique for a programmable logic device (PLD) is disclosed wherein the programmed PLD controls a circuit's behavior according to a desired circuit behavior implementation. A user constructs a program, wherein the program comprises instructions defining inputs, outputs, and conditional branching for an abstract state sequencer that implements the desired circuit behavior. The programming technique then translates the states and resources for the abstract state sequencer into HDL source code, which in turn may be translated into a programming bit pattern for the PLD.

Power sequence controller programming technique

An output block for an in-system programmable analog integrated circuit. The output block features an output amplifier that accepts a differential current-mode input signal and provides a single-ended output voltage. The output amplifier is also selectably operable as a linear amplifier, an integrator or a comparator. The output block also includes a common-mode feedback circuit (CMFB), an analog trim circuit (OATRM), a CLAMP circuit, and an offset calibration circuit (CLDAC), all coupled to the differential input of the output amplifier. The CMFB exhibits bandwidth comparable to that of the output amplifier and a drive capability that enables the differential-input to single-ended output conversion. The CLAMP is connected to the differential input in the comparator mode in order to avoid slow recovery from an overdrive condition. The OATRM forces a difference current into the differential input that compensates for a (gain independent) offset voltage that results from various mismatches. The CLDAC uses a digital-to-analog converter (DAC) to perform offset calibration at the differential input of the output amplifier. In addition, the output block is configured to be operational in a number of user-selectable modes, including, in one embodiment, one or more of: a linear (NORM) mode, a comparator (COMP) mode, and an integrator (INT) mode. An amplifier in the output block is variously reconfigured to achieve the selected mode of operation. Also, the output block accommodates an autocalibration (CAL) technique by clamping the single-ended output stage and balancing, through operation of the CLDAC, signals at an input node and at an interstage node of the amplifier.

Multimode output stage converting differential to single-ended signals using current-mode input signals

Power supply sequencing systems and methods are disclosed. In one embodiment, a programmable charge pump supplies a programmable current source, which drives an external NFET that controls whether power is supplied to a device or a portion of circuitry. The maximum voltage and the turn-on ramp rate supplied to the NFET are programmable and, therefore, the NFET can be operated safely within its rated limits without requiring external protection devices. If a high-voltage output terminal is not required to drive an external NFET, the output terminal, in accordance with another embodiment, may be configured to function as an open drain logic output terminal.

Power supply control circuits

The inventive level shifting circuit shifts an analog input signal by a precise amount. This allows it to be used in precision instrumentation applications where precise signal shifts are critical. It uses a self-biasing feedback circuit to determine the bias current needed to shift an analog signal by a desired amount. The circuit automatically compensates for influences by temperature, supply voltage, and process variations. This circuit also has value as a stand-alone function for other (non-programmable) products.

Precision analog level shifter with programmable options

An improved programmable transconductor can be efficiently implemented utilizing a programmable resistor circuit that allows for only a selected portion of the resistor circuit (associated with a desired transconductor gain) to be coupled between summing nodes of the transconductor. Additional switching circuits can be used to reduce gain errors associated with the switches used to implement the aforementioned solution. Additionally, the improved programmable transconductor can be integrated into fully differential programmable analog integrated circuits, thereby enhancing the performance of such integrated circuits.

Highly linear programmable transconductor with large input-signal range

Provided is an amplifier circuit and method of using the same that features an adjustable resistor network to enable varying the operational characteristics of an amplifier. The resistor network includes primary resistors connected in series with a plurality of adjustment resistors connected to the output of an operational amplifier. A switching network is connected between the resistor network and the input of the operational amplifier. The switching network enables selectively varying the input and feedback resistance of the amplifier circuit to obtain a desired differential gain, while minimizing common-mode gain.

Amplifier having an adjust resistor network

A balanced current amplifier mirrors either a fully differential or single ended input signal into common output circuits in a manner to generate a fully differential output signal without any d.c. bias. Input signal nodes are maintained at a desired voltage by circuit elements other than those of the current mirror circuits, thus freeing the current mirroring elements from having to be sized for this purpose. The sizes of the output transistors are adjustable in order to set the gain of the circuit. In addition to amplifier circuits, a full-wave rectifier, a comparator, and a filter, all operating with current signals, are described. A single circuit module may include all of these circuits with a user provided the capability to program the module to perform any one or more of these functions.

Growing community of inventors

Danville, CA, United States of America

Hans W Klein