Infineon Technologies Ag

International Business Machines Corporation

Hans Viehmann

John Kenneth DeBrosse

Dietmar Gogl

Heinz Hoenigschmid

Stefan Lammers

A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.

Method and apparatus for current sense amplifier calibration in MRAM devices

A circuit configuration for a current switch of a bit line or a word line of a magnetoresistive random access memory (MRAM) device, comprising a directional switch and a voltage driver that, in operation, reduces the ON resistance of the directional switch. In one embodiment, each terminal of the line is provided with such a switch.

Circuit configuration for a current switch of a bit/word line of a MRAM device

It is difficult to fabricate a semiconductor memory device without any faulty memory storage cells. One solution is to produce more storage cells than needed on a device and faulty storage cells are replaced by the redundant storage cells. This solution requires that the addresses of the faulty storage cells, along with the replacement storage cells, be saved in a memory. The present invention teaches the use of non-volatile memory cells, particularly magnetoresistive random access memory (MRAM) cells, to store the addresses. Non-volatile memory cells can effectively replace the laser fuses currently used and also provides an advantage in the elimination of the laser fuse-burning step during the fabrication of the device.

Fuse concept and method of operation

An architecture for a magnetoresistive random access memory (MRAM) storage cell with reduced parasitic effects is presented. An additional runs of metal laid in parallel to both the wordline and the bitlines of the MRAM device provide a write wordline and a write bitline are separated from the wordline and the bitline by a dielectric layer and provides electrical isolation of the write currents from the magnetic stacks. The electrical isolation of the write wordline and bitlines reduces the parasitic capacitance, inductance, and resistance seen by the wordline and bitlines during the write operation. The wordline and bitlines remain as in a standard MRAM cross-point array architecture and is dedicated for reading the contents of the MRAM storage cell.

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S. Burlington, VT, United States of America

Hans Viehmann