International Business Machines Corporation

Hans S Rupprecht

Robert Otto Schwenker

Cheng Tzong Horng

Jerry M Woodall

Ingrid E Magdo

Richard R Konian

Joseph R Cavaliere

Michael R Poponiak

Sandip Tiwari

Robert Rosenberg

Rodney T Hodgson

Thomas N Jackson

John Lawrence Freeouf

George D Pettit

Alan B Fowler

Wei-Kan Chu

Alwin E Michel

Norman Braslau

This invention relates generally to ohmic contacts to substrates made of III-V compounds and to a process for fabricating such contacts. More specifically, the invention is directed to a contact to gallium arsenide having a given level of n-type dopant therein, a region of the substrate doped with germanium and a layer of a germanide of a refractory metal selected from the group consisting of molybdenum, tungsten and tantalum disposed on the substrate. Still more specifically, the invention relates to an ohmic contact to gallium arsenide which includes an interface region of germanium heavily doped with arsenic disposed between the region doped with germanium and the layer of germanide. The contact is formed by evaporating germanium and a refractory metal selected from the group consisting of molybdenum, tungsten and tantalum on the surface of an n-type gallium arsenide substrate and sintering the substrate in a reducing atmosphere for a time and at a temperature sufficient to form the first-to-form germanide of the refractory metal. The resulting contact is stable, has a very low contact resistance and may be subjected to later high temperature processing steps without affecting its characteristics.

High temperature stable ohmic contact to gallium arsenide

Structure of an improved bipolar transistor

Disclosed is a method of making on a common substrate complementary vertical NPN and PNP transistors having matched high performance characteristics. A barrier region of a first conductivity type is formed on a semiconductor substrate of a second conductivity type. Then, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate. In a preferred embodiment the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base. The polycrystalline silicon is doped with a P-type dopant. Thereafter the transistor structure is subjected to conditions whereby the doping ions contained in the polycrystalline silicon layer are driven into the epitaxial layer to provide a shallow emitter region without effecting dislocations in the silicon lattice of the epitaxial layer.

Complementary transistor structure and method for manufacture

Ion implanted impurity activation in a multi-element compound semiconductor crystal such as gallium arsenide, GaAs, over a broad integrated circuit device area, is accomplished using a short time anneal, in the proximity of a uniform concentration of the most volatile element of said crystal, in solid form, over the broad integrated circuit device area surface. A GaAs integrated circuit wafer having ion implanted impurities in the surface for an integrated circuit is annealed in the vicinity of 800.degree.-900.degree. C. for a time of the order of 1-20 seconds in the proximity of a uniform layer of solid arsenic.

Method of activating implanted impurities in broad area compound

A transistor structure is provided with an emitter which is formed from non-monocrystalline silicon which is caused to be converted to monocrystalline silicon during the manufacture of the transistor. In the process of manufacturing the present semiconductor structure, a subcollector is formed in a semiconductor substrate. The subcollector dopant out diffuses into a subsequently deposited epitaxial layer. A base region is formed in the epitaxial layer of a conductivity type opposite that of the conductivity type of the subcollector. This results in a PN junction between the base region and the out diffused subcollector impurities forming the collector of the transistor. A layer of non-monocrystalline silicon is deposited on the epitaxial layer. At least a portion of the non-monocrystalline silicon forms a precursor for an emitter region which is contiguous to but vertically displaced from the surface of the base region. The emitter precursor is then bombarded with ions of a conductivity type that is the same as the conductivity type of the subcollector. The ion bombardment is at a dose and energy level sufficient to displace a portion of the Gaussian distribution of the ions across the interface between the non-monocrystalline layer and the epitaxial layer and into the base region. Thereafter, the structure is annealed by suitable means to drive a portion of the ions deeper into the base region and to convert the non-monocrystalline silicon of the emitter precursor into a monocrystalline emitter region.

Method of making emitter regions by implantation through a

A method for the fabrication of a gallium arsenide (GaAs) metal-semiconductor field effect transistor (MESFET) is described. The method requires the step of providing a semi-insulating GaAs substrate having thereon a layer of n doped GaAs and another layer of n+ doped Ga.sub.1-x Al.sub.x As, the latter being used as a diffusion source for n dopants in selectively doping the n GaAs layer underneath. The fabrication method further includes the step of employing highly directional reactive ion etching on silicon nitride to build insulating side walls thereby to effect the self-alignment of the gate of the MESFET with respect to its source and drain. GaAs MESFET fabricated using this method has its source and drain in close proximity having its gate therebetween. Utilizing the disclosed method, conventional photolithographic techniques can be employed to produce submicron self-aligned GaAs MESFETs.

Self-aligned process for fabricating gallium arsenide

A semiconductor device of the ballistic type, wherein the carrier transport in the body of the device from one electrode to the other takes place essentially free of collisions, is fabricated with a semiconductor body having a long mean-free path, a body width between ohmic electrodes that is less than or equal to the product of the velocity of a carrier and the time to a collision, but more than the distance that will permit quantum mechanical tunnelling, an impressed voltage less than required for an intervalley carrier transition and having the ohmic external contact on each surface of the body free of any barrier to carrier flow. A ballistic type triode device is provided with a current modulating electrode included within the body of the device. The triode device body is of n type conductivity gallium arsenide containing a zinc doped p type conductivity gallium arsenide current modulating inclusion in the body and having, as at least one ohmic external contact, a graded bandgap indium gallium arsenide region.

Semiconductor ballistic transport device

Complementary, vertical bipolar NPN and PNP transistors are fabricated on the same monolithic semiconductor substrate which have matched high performance characteristics. A method for fabricating such complementary devices is also provided. In the method, a barrier region of a first conductivity type is formed on the surface of the monocrystalline semiconductor substrate doped with a second conductivity type. After an annealing heat treatment to drive in the doping ions of the barrier region, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. The collector region for the other complementary transistor is formed within at least one other isolation region. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate. To provide improved PNP transistor performance, the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base. The polycrystalline silicon is doped with a P-type dopant. Thereafter the transistor structure is subjected to conditions whereby the doping ions contained in the polycrystalline silicon layer are driven into the epitaxial layer to provide a shallow emitter region without effecting dislocations in the silicon lattice of the epitaxial layer.

Complementary transistor structure

An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction. Also disclosed is a process and alternative process, for fabricating an improved bipolar transistor structure.

Process for fabricating a bipolar transistor

A method for device fabrication utilizing a self-aligned process. A combination of advanced semiconductor processing techniques including Deep Dielectric Isolation by reactive-ion etching, etching and refilling, planarizing with oxides and resists, and differential thermal oxidation are used to form devices having small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls which extend from the epitaxial silicon surface through the N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3 .mu.m. A shallow oxide trench extends from the epitaxial silicon surface to the upper portion of the N+ subcollector and separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in a low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which is formed by an etch and refill process and which surrounds the emitter and makes lateral contact to the active base.

Process for fabricating a self-aligned micrometer bipolar transistor

Practice of the disclosure reduces thermal decomposition and retains stoichiometry during annealing of a multiple element intermetallic semiconductor material by heating it in an environment with an excess of the most volatile constituent. In particular, practice of the disclosure is obtained by annealing a GaAs wafer with a surface into which Si has been implanted while the surface is in proximity to InAs.

Annealing of ion implanted III-V compounds in the presence of another III-V

A method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3.0 .mu.m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base.

Self-aligned micrometer bipolar transistor device and process

In this process of producing a bipolar transistor, all the regions of the device except the emitter region are formed by ion implantation through an inorganic dielectric layer of uniform thickness. Subsequently, all the contact openings to the emitter, base and collector are formed and the emitter is implanted through the emitter contact opening. This unique combination of process steps permits the use of a surface insulating dielectric layer of uniform thickness, wherein all capacitances are uniform and controllable while still permitting direct implantation of the emitter, which, because of its shallow depth is difficult to implant through an oxide.

Process for producing integrated circuit devices by ion implantation

A method of ion implantation is provided which is particularly applicable to the fabrication of integrated circuits with high current ion implantation apparatus utilizing ion beams having currents of at least 0.5 ma. The method avoids excessive charge buildup on semiconductor wafer surfaces which may destroy the surface electrical insulation, thereby rendering the integrated circuit ineffective. The method involves forming in a layer of electrically insulative material over the wafer, a plurality of openings through the insulative layer in the various chip areas to expose the semiconductor wafer surfaces which are to be ion implanted with conductivity-determining impurities, and in addition, forming openings through the insulative layer over the kerf area between wafer chips to expose wafer kerf adjacent to the chip openings. The total area exposed in the wafer kerf must be greater than the total area exposed in said chip wafer openings. Then, a beam of ions having sufficient energy to implant ions in the exposed wafer in said chip area and kerf openings is directed at the wafer. The presence of the kerf openings avoids the problem of charge buildup. Then, the kerf area is removed by conventional dicing to separate the wafer into a plurality of chips.

Growing community of inventors

Yorktown Heights, NY, United States of America

Hans S Rupprecht