Infineon Technologies Ag

Siemens Aktiengesellschaft

Meyer Burger (Germany) Gmbh

Qimonda Ag

Meyer Burger Gmbh

Hans-Peter Sperlich

Stephan Wege

Peter Baars

Mirko Vogt

Zvonimir Gabric

Markus M Kirchhoff

Oswald Spindler

Joachim Mai

Moritz Haupt

Pierre Papet

Jens Zimmermann

Klaus Dieter Penner

Uwe Schilling

Marcel Koenig

Barbara Lorenz

Andreas Klipp

Wilhelm Claussen

Gunter Erfurt

Gunnar Köhler

Manfred Engelhardt

Heiko Mehlich

Giuseppe Citarella

Gunnar Koehler

Momtchill Stavrev

Daniel Decker

Thomas Grosse

Frank Wuensch

Hermann Schlemm

Marcel König

Hans Glawischnig

Detlef Sontag

Daniel Köhler

Volker Gajewski

Frank Wünsch

Mirko Mehlich

Michael Grimm

König Marcel

A monofacial or bifacial crystalline solar cell, on the front face of which over the entire area a first surface passivation layer is arranged directly on the semiconductor interface and above this a first optically opaque, electrically conductive material is arranged in first lateral regions as a front face contact, and a first optically transparent, electrically conductive material is arranged exclusively in second lateral regions. The first optically transparent, electrically conductive material is electrically conductively connected to the front face contact and to a first region of the semiconductor material of the solar cell. The method provides for application of the first optically transparent, electrically conductive material only after the first optically opaque, electrically conductive material has been applied, in such a way that firing of the front face contact is avoided.

Crystalline solar cell comprising a transparent, conductive layer between the front-side contacts and method for producing such a solar cell

A solar cell with a heterojunction is produced. A first amorphous nano- and/or microcrystalline semiconductor layer is formed on the front face of a crystalline semiconductor substrate to form front face emitter or a front face surface field layer. A second such layer is formed on the rear face of the substrate to form a rear face surface field layer or a rear face emitter. Electrically conductive, transparent front face and rear face electrode layers and a frontal metallic contact layer grid structure are formed. Surface selective frontal PECVD deposition forms an electrically non-conductive, transparent dielectric front face cover layer and with such a thickness to form a closed layer directly on deposition, without additional heat and/or chemical treatment, only on the areas surrounding the frontal contact layer grid structure but not on the frontal contact layer grid structure. Finally, a rear face metallization is formed.

Method for producing a solar cell, solar cell produced by this method and substrate carrier

An integrated circuit device includes a substrate with a first layer situated on the substrate. The first layer defines a first opening with a cover layer deposited on the first layer and coating a sidewall portion of the first opening. A second layer is situated on the cover layer. The second layer defines a second opening extending through the second layer and through the cover layer to connect the first and second openings.

Integrated circuit device having openings in a layered structure

The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (); providing and patterning a silicon nitride layer () on the semiconductor substrate () as topmost layer of a trench etching mask; forming a trench () in a first etching step by means of the trench etching mask; conformally depositing a liner layer () made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (); carrying out a V plasma etching step for forming a V profile of the line layer () in the trench (); wherein the liner layer () is pulled back to below the top side of the silicon nitride layer (); an etching gas mixture comprises CF, Oand an inert gas is used in the V plasma etching step; the ratio (V) of CF/Olies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.

Fabrication method for a semiconductor structure

A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.

Deposition of various base layers for selective layer growth in semiconductor production

A method for the treatment of objects, preferably wafers, in a corresponding apparatus. The apparatus having at least two or more process chambers for receiving and treating the objects as well as a handling apparatus, for example a robot arm, for loading and unloading the process chambers. To date, all the process chambers have been loaded with the objects directly in succession. Accordingly, the actual treatment begins virtually simultaneously in all the process chambers. Furthermore, the necessary cleaning processes in the process chambers are also carried out virtually simultaneously. In order to increase the throughput of objects to be treated and to prevent or to minimize the overlapping of the cleaning processes, the invention proposes that, at the program start, at the beginning of the treatment method, the loading of the objects into the first process chamber and beginning of the treatment of the objects are effected, and that, subsequently, temporally staggered initial loading of the objects into the second process chamber and beginning of the treatment of the objects are effected. The temporally staggered initial loading of the individual process chambers can be effected by manual or computer-aided control of the apparatus. Furthermore, a corresponding apparatus is described.

Method and apparatus for the treatment of objects, preferably wafers

The fabrication method provides for an etched isolation trench to be lined, if appropriate firstly with a thin thermal oxide layer, and then with an oxidizable auxiliary layer. The auxiliary layer consumes oxygen during subsequent thermal processes, thereby avoiding oxidation of deeper structures, in particular of an insulation collar in a capacitor trench.

Method for fabricating an isolation trench using an auxiliary layer

An antireflection layer, preferably a dielectric antireflection layer, is applied by PECVD to a hard mask layer which is composed of doped silicon oxide, with no interruption of the vacuum. The silicon oxide layer is then patterned to form a hard mask and, by way of example, a deep trench etching is performed. The hard mask is removed using an HF/H,SO,mixture or using an HF/ethylene glycol (EG) mixture at a high etching rate. If the HF/EG mixture is used, an intermediate layer that may be disposed underneath can simultaneously be etched back by a predetermined amount. The integration of two wet etching steps constitutes a major simplification compared with the previous wet etching methods in two different installations.

Method for fabricating a semiconductor structure

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Dresden, Germany

Hans-Peter Sperlich