Infineon Technologies Austria Ag

Infineon Technologies Ag

Hans Peter Felsl

Hans-Joachim Schulze

Franz Hirler

Franz-Josef Niedernostheide

Maria Cotorogea

Frank Dieter Pfirsch

Thomas Raker

Oliver Haeberlen

Gerhard Prechtl

Clemens Ostermaier

Holger Schulze

Elmar Falck

Manfred Pfaffenlehner

Andre Rainer Stegner

Anton Mauder

Francisco Javier Santos Rodriguez

Frank Hille

Moriz Jelinek

Daniel Schloegl

Thomas Gutt

Frank Umbach

Andreas Haertl

Wolfgang Wagner

Volodymyr Komarnitskyy

Konrad Schraml

Yvonne Gawlina

Wolfgang Roesener

Georg Seibert

A power semiconductor transistor includes a semiconductor body having a front side and a backside with a backside surface. The semiconductor body includes a drift region of a first conductivity type and a field stop region of the first conductivity type. The field stop region is arranged between the drift region and the backside and includes, in a cross-section along a vertical direction from the backside to the front side, a concentration profile of donors of the first conductivity type that has: a first local maximum at a first distance from the backside surface, a front width at half maximum associated with the first local maximum, and a back width at half maximum associated with the first local maximum. The front width at half maximum is smaller than the back width at half maximum and amounts to at least 8% of the first distance.

Power semiconductor transistor

A semiconductor diode includes a semiconductor body having opposite first and second sides. A first and a second semiconductor region are consecutively arranged along a lateral direction at the second side. The first and second semiconductor regions are of opposite first and second conductivity types and are electrically coupled to an electrode at the second side. The semiconductor diode further includes a third semiconductor region of the second conductivity type buried in the semiconductor body at a distance from the second side. The second and third semiconductor regions are separated from each other.

Semiconductor diode and method of manufacturing a semiconductor diode

A method of manufacturing a transistor device includes forming a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure, the 2DEGs forming current channels of the transistor device, forming a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels, forming a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels, and forming a plurality of spaced apart gate structures extending into the semiconductor heterostructure and including an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material.

Method of manufacturing a multi-channel HEMT

A semiconductor device has a semiconductor body with bottom and top sides and a lateral surface. An active semiconductor region is formed in the semiconductor body and an edge region surrounds the active semiconductor region. A first semiconductor zone of a first conduction type is formed in the edge region. An edge termination structure having at least N field limiting structures is formed in the edge region. Each of the field limiting structures has a field ring and a separation trench formed in the semiconductor body, where N is at least 1. Each of the field rings has a second conduction type, forms a pn-junction with the first semiconductor zone and surrounds the active semiconductor region. For each of the field limiting structures, the separation trench of that field limiting structure is arranged between the field ring of that field limiting structure and the active semiconductor region.

Semiconductor device with a field ring edge termination structure and a separation trench arranged between different field rings

A method of manufacturing a semiconductor device includes forming a semiconductor diode by forming a drift region, forming a first semiconductor region of a first conductivity type in or on the drift region and electrically coupling the first semiconductor region to a first terminal via a first surface of a semiconductor body, etching a trench into the semiconductor body, and forming a channel region of a second conductivity type in the trench and electrically coupling the channel region to the first terminal via the first surface of the semiconductor body. A first side of the channel region adjoins the first semiconductor region.

Method for manufacturing a semiconductor device having a channel region in a trench

A transistor device includes a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure. The 2DEGs form current channels of the transistor device. The transistor device further includes a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels, and a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels. The transistor device also includes a plurality of spaced apart gate structures extending into the semiconductor heterostructure and including an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material.

Multi-channel HEMT

A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Semiconductor device having a floating semiconductor zone

A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.

Semiconductor device including trenches and method of manufacturing a semiconductor device

A method for manufacturing a semiconductor device by laser annealing. One embodiment provides a semiconductor substrate having a first surface and a second surface. The second surface is arranged opposite to the first surface. A first dopant is introduced into the semiconductor substrate at the second surface such that its peak doping concentration in the semiconductor substrate is located at a first depth with respect to the second surface. A second dopant is introduced into the semiconductor surface at the second surface such that its peak doping concentration in the semiconductor substrate is located at a second depth with respect to the second surface, wherein the first depth is larger than the second depth. At least a first laser anneal is performed by directing at least one laser beam pulse onto the second surface to melt the semiconductor substrate, at least in sections, at the second surface.

Method for manufacturing a semiconductor substrate including laser annealing

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Munich, Germany

Hans Peter Felsl