At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Hans P Graf

Richard E Howard

Lawrence David Jackel

Donnie Henderson

John Stewart Denker

Lawrence O'Gorman

Wayne E Hubbard

A measure of the correlation or degree of closeness between an input data pattern and a stored data pattern is achieved directly from content-addressable memory cells which are realized in accordance with the principles of the present invention to provide a match/non-match output indication which is summable with other such match/non-match output indications on a match bus line for computing the correlation or degree of closeness measure. Each content-addressable memory cell includes a single bit, static random access memory cell and a comparing logic gate connected jointly to the output of the static random access memory cell and the bit bus line for the single bit of the input data pattern. Output of the comparing logic gate is connected to the match bus line and is generated as a fixed amount of current which can be summed with other current on the match bus line. The output stage of the comparing gate is thus operated as a current source. Each content-addressable memory cell accepts digital input signals and delivers a usable analog output signal. In one embodiment, the content-addressable memory cell is realized in a complementary metal oxide semiconductor technology and the comparing logic gate is an exclusive-NOR gate.

Content-addressable memory

A method for improved thinning or skeletonizing handwritten characters or other variable-line-width images. The method scans a template set over the image to be thinned. Each template has a specific arrangement of dark and light pixels. At least one of those templates includes either more than three pixels per row or more than three rows of pixels. An odd number is good choice. Moreover, the templates are chosen so that each template can unconditionally delete image pixels without consideration of the effect of such deletions on the behavior of the other templates. Thus the templates are independent of each other.

Image skeletonization method

Realization of a reconfigurable neuron for use in a neural network has been achieved using analog techniques. In the reconfigurable neuron, digital input data are multiplied by programmable digital weights in a novel connection structure whose output permits straightforward summation of the products thereby forming a sum signal. The sum signal is multiplied by a programmable scalar, in general, 1, when the input data and the digital weights are binary. When the digital input data and the digital weights are multilevel, the scalar in each reconfigurable neuron is programmed to be a fraction which corresponds to the bit position in the digital data representation, that is, a programmable scalar of 1/2, 1/4, 1/8, and so on. The signal formed by scalar multiplication is passed through a programmable build out circuit which permits neural network reconfiguration by interconnection of one neuron to one or more other neurons. Following the build out circuit, the output signal therefrom is supplied to one input of a differential comparator for the reconfigurable neuron. The differential comparator receives its other input from a supplied reference potential. In general, the comparator and reference potential level are designed to generate the nonlinearity for the neuron. One common nonlinearity is a hard limiter function. The present neuron offers the capability of synthesizing other nonlinear transfer functions by utilizing several reference potential levels connected through a controllable switching circuit.

Reconfigurable neural network

A new associative computation network that is capable of storing multi-bit vectors includes a decision network and a feedback arrangement that, functionally, is separable into serially connected networks. The first network has its inputs connectd to the outputs of the decision network and is arranged to develop sets of excitatory and inhibitory drive signals. Each set corresponds to a stored vecor. For each different output state of the decision network, a different one of the drive signal sets appears at the output of the first network. The output leads of the first network, which may also be employed as the input interface leads, are connected to the second network. The second network develops output signals, applied to inputs of the decision network, which are proportional to the projection of the input signals applied to the second network on the stored vectors.

Computational network

The operation of neural networks begins with the initialization of the system with the information to be processed. Presently, this initialization is performed by pinning the system with rather large analog or digital signals representing this information. The problems associated with the high power required for such initialization are eliminated and accuracy is maintained by utilizing a specific set of input points and appropriately positioned switches. In particular, a switch corresponding to each amplifier is introduced, and the initializing data is introduced between the amplifier and this switch.

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East Keansburg, NJ, United States of America

Hans P Graf