Infineon Technologies Ag

Infineon Technologies Wireless Solutions Sweden Ab

Hans Norström

Ted Johansson

Karin Andersson

Anders Lindgren

Stefan Sahl

Patrick Algotsson

Patrik Algotsson

A method for producing vertical bipolar transistors having different voltage breakdown and high-frequency performance characteristics on a single die comprises forming, for each of the vertical bipolar transistors, a buried collector region, and base and emitter regions above the buried collector region. The lateral extensions and locations of the base and emitter regions and of the buried collector region are, for each of the vertical bipolar transistors, selected to create an overlap between the base and emitter regions, and the buried collector region, as seen from above, wherein at least some of the overlaps are selected to be different.

Method for producing vertical bipolar transistors and integrated circuit

A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n-type region; forming field isolation areas around the n-type region; forming a PMOS gate region on the n-type region; forming a diffused n-type contact from the upper surface of the substrate to the buried n-type region; the contact being separated from the n-type region; forming a p-type polysilicon source on the n-type region; forming a p-type source in the n-type region; forming a p-type drain in the n-type region; and connecting the PMOS transistor structure to operate as a PNP transistor, wherein the source is connected to the gate and constitutes an emitter of the PNP transistor; the drain constitutes a collector of the PNP transistor; and the n-type region constitutes a base of the PNP transistor.

Semiconductor fabrication process, lateral PNP transistor, and integrated circuit

A monolithically integrated circuit comprises a thin film resistor () with low resistance and low temperature coefficient; a high frequency lateral power transistor device () including gate (), source () and drain () regions, and a Faraday shield layer region (') above the gate region; and at least a first metallization layer () there above for electrical connection of the gate (), source () and drain () regions through via holes filled with conductive material (). The thin film resistor () and the Faraday shield layer region (&#x2032;) are made in the same conductive layer, which is arranged below the first metallization layer ().

Monolithically integrated circuit comprising a thin film resistor, and fabrication method thereof

A method in the fabrication of an integrated bipolar circuit for forming a p/n-junction varactor is disclosed. The method featuring the steps of providing a p-doped substrate (); forming a buried n-doped region () in the substrate; forming in the substrate an n-doped region () above the buried n-doped region (); forming field isolation () around the n-doped region (); multiple ion implanting the n-doped region (); forming a p-doped region () on the n-doped region (); forming an n-doped contact region to the buried n-doped region (), the contact region being separated from the n-doped region (); and heat treating the hereby obtained structure to set the doping profiles of the doped regions. The multiple ion implantation of the n-doped region (); the formation of the p-doped region (); and the heat treatment are performed to obtain a hyper-abrupt p/n-junction within the n-doped region ().

Fabrication method, varactor, and integrated circuit

A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition.

Method to provide a triple well in an epitaxially based CMOS or BiCMOS process

A method in the fabrication of a silicon-germanium mesa transistor in a semiconductor process flow comprises the steps of providing a p-type doped silicon bulk substrate () having an n-type doped surface region () being a subcollector; depositing epitaxially thereon a silicon layer () comprising n-type dopant; depositing epitaxially thereon a silicon layer () comprising germanium and p-type dopant; forming in the epitaxial layers () field isolation areas () around, in a horizontal plane, a portion of the epitaxial layers () to simultaneously define an n-type doped collector region () on the subcollector (); a p-type doped base region () thereon; and an n-type doped collector plug on the subcollector (), but separated from the n-type doped collector region () and the p-type doped base region (); and forming in the p-type doped base region () an n-type doped emitter region.

Silicon-germanium mesa transistor

In a bipolar double-poly transistor comprising a layer of base silicon (') on a silicon substrate (&#x2032;), a first layer of silicon dioxide (&#x2032;) on the base silicon layer (&#x2032;), an emitter window (&#x2032;) extending through the first layer (&#x2032;) of silicon dioxide and the base silicon layer (&#x2032;), a second layer (&#x2032;) of silicon dioxide in the emitter window (&#x2032;), silicon nitride spacers (&#x2032;) on the second layer (&#x2032;) of silicon dioxide in the emitter window (&#x2032;), and emitter silicon (&#x2032;) in the emitter window (&#x2032;), an isolating silicon nitride seal is provided to separate the base silicon (&#x2032;) from the emitter silicon (&#x2032;) to prevent short-circuiting between the base silicon (&#x2032;) and the emitter silicon (&#x2032;) in the transistor.

Arrangement for preventing short-circuiting in a bipolar double-poly transistor and a method of fabricating such an arrangement

A method for selective etching in the manufacture of a semiconductor device comprises: forming a layer () of silicon-germanium on a substrate () of monocrystalline silicon or on a substrate at least comprising a surface layer of monocrystalline silicon, depositing at least a dielectric layer () on the silicon-germanium layer () and patterning the resultant structure (), whereafter the dielectric layer () and the silicon-germanium layer () are etched away within a predetermined region (). Preferably, the silicon-germanium layer () is amorphous, whereby the dielectric layer () is deposited on the amorphous silicon-germanium layer () in such a manner to prevent crystallization of the amorphous layer. After etching the structure may be heat-treated such that the amorphous layer crystallizes. The method is preferably applicable for etching an emitter window in the manufacture of a bipolar transistor having a self-registered base-emitter structure.

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Solna, Sweden

Hans Norström