Telefonaktiebolaget Lm Ericsson (publ)

Hans Norstr&ouml;m

Ted Johansson

Carl Bj&ouml;rmander

Ola Knut Tylstedt

Anders Lindgren

Torkel Bengt Arnborg

Stefan Nygren

Tomas Jarstad

A method for forming an electrical device structure in an integrated circuit comprises providing a substrate; forming a passivation layer thereon; forming a plurality of through holes in the passivation layer, the through holes; removing substrate material under the passivation layer by means of isotropic etching, thus forming at least a first cavity in the substrate beneath the plurality of through holes; forming a dielectric layer on top of the passivation layer to plug the through holes, thereby creating a membrane; and creating an electrical device, such as e.g. an inductor, above the membrane.

Integrated circuit inductor structure and non-destructive etch depth measurement

In an integrated circuit, particularly an integrated circuit for radio frequency applications, a semiconductor structure for isolation of semiconductor devices that includes a semiconductor substrate, at least one shallow trench extending vertically into the substrate, a deep trench laterally located within the shallow trench, where the deep trench extends vertically further into the substrate. The deep trench is self aligned to the shallow trench with a controlled lateral distance between an edge of the shallow trench and an edge of the deep trench and the lateral extensions of the shallow and deep trenches, respectively, are independently chosen.

Semiconductor structure for isolation of semiconductor devices

In order to produce an electrical connection to an inner layer such as a bottom diffusion ( ), which has a good electrical conductivity and is located inside a bipolar semiconductor device isolated by trenches ( ) and which for example forms a subcollector of a NPN-transistor, a hole ( ) in a trench is used. The hole is filled with electrically conducting material and extends from the surface of the device to the bottom diffusion ( ), so that the electrically conducting material in the hole is in contact therewith. The hole ( ) is made aligned with a sidewall of the trench ( ) by using selective etching. The hole can be made at the same time as contact holes for metallization are made and then also be filled in the metallization step, to contact the bottom diffusion. For a lateral PNP-transistor the hole can be made as a closed groove constituting the outer confinement of the base area, passing all around the transistor. The outer sidewall of such a closed trench can, as seen from above, be bevelled by 45&deg;, so that no inner corners having too small angles are found in the trench, what facilitates the filling with oxide.

Trench-isolated bipolar devices

A bipolar transistor of type NPN has an active region at the surface of the component, which is surrounded, as seen along the surface of the component, in the conventional way by thick field oxide areas. The active region is partly covered by an electrically isolating surface layer, preferably comprising a nitride layer. A base region in the active region is defined by a well-defined opening, which is lithographically produced, in the electrically isolating surface layer. For a bipolar lateral transistor of type PNP, which instead has emitter and collector regions surrounded by such thick field oxide areas, the emitter and collector regions can in the corresponding way be defined by a lithographically defined opening in an electrically isolating surface layer. Owing to the well defined openings the base-collector capacitance and the emitter-collector capacitance respectively can be reduced in these cases, what results in better high frequency characteristics of the transistors. A region of the silicon nitride layer is at the same time used as an efficient dielectric in a simultaneously manufactured capacitor. The NPN-transistor can be provided with a thin side string made of nitride for isolation between an emitter connection and a base connection. In the same semiconductor plate special, deep and shallow substrate connecting terminals can be provided for electrically isolating component areas. Trenches can be used for electrical isolation of component areas and they can at their sidewalls have a laminate of at the bottom oxide and thereon nitride in order to facilitate planarizing etching and in order to act as a diffusion barrier.

Methods of manufacturing bipolar transistors for use at radio frequencies

In the fabrication of a transistor device, particularly a low-voltage high-frequency transistor for use in mobile telecommunications, a method for improving the transistor performance and the high-frequency characteristics of the device is described. The method includes providing a semiconductor substrate ( ) with an n-doped collector layer ( ) surrounded by isolation areas ( ), implanting antimony ions into the collector layer such that a thin highly n-doped layer ( ) is formed in the uppermost portion of the collector layer, and forming a base on top of said thin highly n-doped layer ( ).

Transistor device and fabrication method thereof

Apparatus and methods for manufacturing low-resistant substrate contacts in integrated circuits are disclosed. The contacts are low resistive conducting plugs and are located outside the areas of active components. The substrate is connected from the top portion in order to obtain a low resistance. Multiple metal plugs electrically interconnect the substrate of the integrated circuit with the top portion of the integrated circuit.

Substrate contacts and shielding devices in a semiconductor component

A method to improve the characteristics of bipolar silicon high-frequency transistor by adding indium into the base of the transistor is described. Instead of replacing boron in the base with indium to improve the beta-Early voltage product, at the price of high beta and high base resistance, separate boron and indium doping profiles are combined in the base. Thus, a transistor, which preserves most of the properties of pure boron-base transistor, is obtained, but with some parameters improved due to the added indium profile. This &ldquo;double-profile&rdquo; or &ldquo;indium-enhanced&rdquo; transistor exhibits improved beta-Early voltage product, reduced collector-base capacitance swing and lower temperature dependence of beta, but preserves the advantageous properties of a pure boron-base transistor. For this to work satisfactory, the indium profile must be contained within the boron profile in such a way that the beta and the effective base width are not significantly affected, otherwise the high frequency properties will be degraded. A typical process for fabricating a bipolar silicon high frequency NPN transistor together with some recorded parameters highlighting the benefits of an additional indium implant is presented.

Indium-enhanced bipolar transistor

In the fabrication of a silicon bipolar transistor, a method for forming base regions and for opening an emitter window is provided. A silicon substrate is provided with suitable device isolation. A first base region is formed in or on top of the substrate. A thin layer of oxide is formed on the first base region. A layer of silicon is formed on top of the thin oxide layer, the silicon layer is to be a second base region. The silicon layer is ion implanted. A layer of a dielectric is formed on top of the silicon layer, the dielectric is to isolate base and emitter regions of the transistor. The obtained structure is patterned in order to define the emitter window. The structure inside the defined emitter window area is etched and through the dielectric and silicon layers, wherein the thin oxide layer is used as etch stop, thus forming the emitter window. The structure is subsequently heat treated and thus break up the oxide such that the first and second base regions will contact each other.

Method in the fabrication of a silicon bipolar transistor

In the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, a method for forming shallow and deep trenches for isolation of semiconductor devices comprised in said circuit, comprising providing a semiconductor substrate; optionally forming a first dielectric layer on said substrate; forming at least one shallow trench by using a first mask, said shallow trench extending into said substrate; forming a second dielectric layer of a predetermined thickness on the structure obtained subsequent to the step of forming at least one shallow trench; forming at least one opening in said second dielectric layer by using a second mask with an edge of said second mask aligned to an edge of said shallow trench with a maximum misalignment of half the predetermined thickness, said opening extending within the shallow trench to the bottom thereof, whereby a spacer of a width equal to the predetermined thickness is formed in said shallow trench and along said edge thereof; and forming a deep trench in said opening by using said second dielectric layer as a hard mask, said deep trench extending further into said substrate and being self-aligned to said shallow trench.

Semiconductor structure and fabrication method of shallow and deep trenches

A selective etching method in the fabrication of a semiconductor device is provided. The method involves the steps of: depositing an amorphous layer of semiconductor material on a monocrystalline substrate of the same semiconductor material; depositing at least one dielectric layer on the amorphous layer such as to prevent crystallization of said amorphous layer; patterning the resultant structure and thereafter etching away the dielectric layer and the amorphous semiconductor layer within a predetermined area or region; and heat-treating the resulting structure.

Growing community of inventors

Solna, Sweden

Hans Norström

Growing community of inventors

Solna, Sweden

Hans Norstr&ouml;m

Hans Norström