Nxp B.v.

Imec Vzw

Hans Mertens

Tony Vanhoucke

Johannes Josephus Theodorus Marinus Donkers

Evelyne Gridelet

Blandine Duriez

Petrus Hubertus Cornelis Magnee

Kurt Wostyn

Philippe Meunier-Beillard

Boon Teik Chan

Liesbeth Witters

Eugenio Dentoni Litta

Gaspard Hiblot

Naoto Horiguchi

Gilberto Curatola

Viet Thanh Dinh

Michiel Jos Van Duuren

Zsolt Tokei

Dusan Golubovic

Guillaume Boccardi

Julien Jussot

Sylvain Baudot

Andriy Hikavyy

Yusuke Oniki

Johannes Theodorus Marinus Donkers

Evelyne Marie Josephe Fabienne Gridelet

A method is provided for forming a semiconductor device. The method includes: forming a device layer stack on a substrate, the device layer stack comprising a bottom sacrificial layer and an alternating sequence of upper sacrificial layers and channel layers; forming a sacrificial gate structure; etching through at least the upper sacrificial and channel layers of the device layer stack while using the sacrificial gate structure as an etch mask; forming a sacrificial spacer covering end surfaces of the upper sacrificial and channel layers; while the sacrificial spacer masks the end surfaces of the upper sacrificial and channel layers, further etching the device layer stack to remove the bottom sacrificial layer and thereby form a cavity in the device layer stack; forming a dielectric layer in the cavity, wherein forming the dielectric layer comprises depositing and then etching back a dielectric bottom material to a level below a bottom-most one of the channel layers; removing the sacrificial spacer; forming recesses and forming inner spacers in the recesses; and forming source and drain regions by epitaxially growing semiconductor material on the end surfaces of the channel layers.

Method for forming a semiconductor device

A method for forming a semiconductor device is provided. The method comprises forming a device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over the topmost channel layer, wherein the top sacrificial layer is thicker than each lower sacrificial layer; etching the top sacrificial layer to form a top sacrificial layer portion underneath the sacrificial gate structure; forming a first spacer on end surfaces of the top sacrificial layer portion; etching the channel and lower sacrificial layers while using the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions; etching the lower sacrificial layer portions to form recesses in the device layer stack, while the first spacer masks the end surfaces of the top sacrificial layer portion; and forming a second spacer in the recesses.

According to an aspect of the present inventive concept there is provided a method for forming source/drain contacts, the method comprising:

Method for forming a semiconductor device and a semiconductor device

Example embodiments relate to counteracting semiconductor material loss during semiconductor structure formation. One embodiment includes a method for forming a semiconductor structure. The method includes providing a structure. The structure includes a substrate. The structure also includes a layer stack on the substrate. The layer stack includes at least one semiconductor layer of a semiconductor material and at least one sacrificial layer under the semiconductor layer. Further, the structure includes a trench through the layer stack. The further also includes forming a recess in the layer stack by etching a portion of the sacrificial layer exposed by the trench. The etching includes a preferential etch of the sacrificial layer with respect to the semiconductor layer. Additionally, the method includes epitaxially growing a liner of the semiconductor material onto surfaces of the semiconductor layer exposed by the trench.

Counteracting semiconductor material loss during semiconductor structure formation

A method of forming aligned gates for horizontal nanowires or nanosheets, comprising: providing a wafer which comprises at least one fin of sacrificial layers alternated with functional layers, and a dummy gate covering a section of the fin between a first end and a second end; at least partly removing the sacrificial layers at the first end and the second end thereby forming a void between the functional layers at the first and end such that the void is partly covered by the dummy gate; providing resist material which oxidizes upon EUV exposure; exposing the wafer to EUV light; selectively removing the dummy gate and the unexposed resist; forming a gate between the functional layers and between the exposed resist at the first end and at the second end.

Self-aligned internal spacer with EUV

The present disclosure relates to a method of forming a semiconductor device comprising horizontal nanowires. The method comprises depositing a multilayer stack on a substrate, the multilayer stack comprising first sacrificial layers alternated with layers of nanowire material; forming at least one fin in the multilayer stack; applying an additional sacrificial layer around the fin such that a resulting sacrificial layer is formed all around the nanowire material; and forming a nanowire spacer, starting from the resulting sacrificial layer, around the nanowire material at an extremity of the nanowire material. The present disclosure also relates to a corresponding semiconductor device.

Horizontal nanowire semiconductor devices

A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

Internal spacers for nanowire semiconductor devices

The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.

Internal spacer formation for nanowire semiconductor devices

Disclosed is a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate () comprising a pair of first isolation regions () separated from each other by an active region () comprising a collector impurity said bipolar transistor; forming a base layer stack (') over said substrate; forming a further stack of a migration layer () having a first migration temperature and an etch stop layer () over said base layer stack (); forming a base contact layer () having a second migration temperature over the further stack, the second migration temperature being higher than the first migration temperature; etching an emitter window () in the base contact layer over the active region, said etching step terminating at the etch stop layer; at least partially removing the etch stop layer, thereby forming cavities () extending from the emitter window in between the base contact layer and the redistribution layer; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material. An IC comprising such a bipolar transistor is also disclosed.

Method of manufacturing IC comprising a bipolar transistor and IC

Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor.

Method of processing a silicon wafer and a silicon integrated circuit

Consistent with an example embodiment, there is method of manufacturing a bipolar transistor comprising providing a substrate including an active region; depositing a layer stack; forming a base window over the active region in said layer stack; forming at least one pillar in the base window, wherein a part of the pillar is resistant to polishing; depositing an emitter material over the resultant structure, thereby filling said base window; and planarizing the deposited emitter material by polishing. Consistent with another example embodiment, a bipolar transistor may be manufactured according to the afore-mentioned method.

Method of manufacturing a bipolar transistor and bipolar transistor

A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.

Tunnel field effect transistor

Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate () comprising a first isolation region () separated from a second isolation region by an active region () comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer ('), a silicon capping layer () over said base layer and a silicon-germanium (SiGe) base contact layer () over said silicon capping layer; etching the SiGe base contact layer to form an emitter window () over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers () in the emitter window; and filling the emitter window with an emitter material (). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.

Bipolar transistor manufacturing method, bipolar transistor and integrated circuit

A method of manufacturing an integrated circuit comprising bipolar transistors including first and second type bipolar transistors, the method comprising providing a substrate comprising first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of the bipolar transistors; forming a base layer stack over the substrate; forming a first emitter cap layer of a first effective thickness over the base layer stack in the areas of the first type bipolar transistor; forming a second emitter cap layer of a second effective thickness different from the first effective thickness over the base layer stack in the areas of the second type bipolar transistor; and forming an emitter over the emitter cap layer of each of the bipolar transistors. An IC in accordance with this method.

Method of manufacturing an IC comprising a plurality of bipolar transistors and IC comprising a plurality of bipolar transistors

Disclosed is a method of manufacturing a heterojunction bipolar transistor comprising a substrate, an upper region of said substrate comprising an active region of the bipolar transistor bordered by shallow trench insulation, said active region comprising a buried collector region extending to a depth beyond the depth of the shallow trench insulation, the method comprising forming a trench in the substrate adjacent to said active region, said trench extending through the shallow trench insulation; at least partially filling said trench with an impurity; and forming a collector sinker in the substrate by developing said impurity to extend into the substrate to a depth beyond the depth of the shallow trench insulation. An IC comprising a heterojunction bipolar transistor manufactured by this method is also disclosed.

Growing community of inventors

Leuven, Belgium

Hans Mertens