Nxp B.v.

Nexperia B.v.

Hans-Martin Ritter

Jochen Wynants

Steffen Holland

Frank Burmeister

Godfried Henricus Josephus Notermans

Wolfgang Schnitt

Zhihao Pan

Joachim Utzig

Achim Werner

Klaus Reimann

Anco Heringa

Friedrich E Hahn

Tobias Sprogies

Thomas Igel-Holtzendorff

Horst Roehm

Olaf Pfennigstorf

Rainer Mintzlaff

Ingo Laasch

Tamim Peter Sidiki

Andreas Zimmerman

Robert Muir Gemmel Izat

Rob P Weber

Martin Lübbe

A semiconductor device structure and method of manufacturing a semiconductor device is provided. The method includes providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, with the second semiconductor substrate including a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming device contacts on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.

Semiconductor device

A semiconductor device arrangement and a method of operating a semiconductor device arrangement. The semiconductor device can be arranged for bidirectional operation. The semiconductor device arrangement can comprise: a field effect transistor comprising first and second input terminals; a control terminal; a first diode connected between the first terminal and the control terminal; and a second diode connected between the second terminal and the control terminal; wherein the first terminal and the second terminal are configured and arranged to be connected to respective signal lines.

Multi-diode semiconductor device and method of operation therefor

A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a semiconductor layer located on the substrate; at least one shallow trench and at least one deep trench. Each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer. Sidewall regions and base regions of the trenches comprise a doped trench region and the trenches are at least partially filled with a conductive material contacting the doped region. The shallow trenches terminate in the semiconductor layer and the deep trench terminates in the semiconductor substrate.

Multi-trench semiconductor device and method of manufacture thereof

A semiconductor device and a method of making the same. The device includes a semiconductor substrate provided in a chip-scale package (CSP). The device also includes a plurality of contacts provided on a major surface of the substrate. The device further includes an electrically floating metal layer forming an ohmic contact on a backside of the semiconductor substrate. The device is operable to conduct a current that passes through the substrate from a first of said plurality of contacts to a second of said plurality of contacts via the metal layer on the backside.

Various aspects of the disclosure are directed to circuitry that may be used to shunt current. As may be consistent with one or more embodiments a first circuit has a plurality of alternating p-type and n-type semiconductor regions with respective p-n junctions therebetween, arranged between an anode end and a cathode end. A second (e.g., bypass) circuit is connected to one of the alternating p-type and n-type semiconductor regions, and forms a further p-n junction therewith. The second circuit operates to provide carrier flow, which influences operation of the first circuit.

Carrier bypass for electrostatic discharge

A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.

Semiconductor substrate with electrically isolating dielectric partition

A common mode choke comprising a first planar coil for receiving a first signal, a second planar coil for receiving a second signal, the first and second coils comprising substantially mirror images of one another and arranged side by side in a common plane, the first planar coil and second planar coil electromagnetically coupled by a closed coupling loop.

Common mode choke

A method of making a plurality of semiconductor devices comprising a chip scale packages. The method includes providing a semiconductor wafer having a major surface and a backside. The method also includes forming a plurality of contacts on the major surface. The method further includes forming a plurality of trenches in the major surface of the substrate. The method also includes forming a plurality of openings in the wafer between the backside and the trenches in the major surface. The method further includes depositing an encapsulant on the backside of the wafer. At least some of the encapsulant passes through the openings in the wafer to at least partially fill the trenches in the major surface. The method also includes singulating the wafer to produce a plurality of chip scale packages having a major surface including one or more contacts and side walls at least partially covered with said encapsulant.

Method of making a plurality of semiconductor devices

The disclosure relates to a data transmission system () comprising a signal line () and a ground line (). A first signal path () is provided between the signal line () and the ground line (). The first signal path () comprises a Shockley diode () having a cathode () and an anode (). The cathode () is connected to the ground line () and the anode () is connected to the signal line ().

Data transmission system

Various embodiments relate to a light emitting diode protection circuit, including: a plurality of diodes connected in series; an input connected to a first diode of the plurality of diodes; an output; a first resistor connected between the plurality of diodes and the output; a transistor with a gate connected to a junction between the first resistor and the plurality of diodes and a source connected to the output; a second resistor connected between the input and drain of the transistor; and a silicon controlled rectifier (SCR) with an anode connected to the input, a base connected to the drain of the transistor, and a cathode connected to the output.

CMOS adjustable over voltage ESD and surge protection for LED application

The present disclosure relates to an electrostatic discharge (ESD) protection device. The electrostatic discharge protection device, may comprise: a semiconductor controlled rectifier; and a p-n diode. The semiconductor controlled rectifier and the diode may be integrally disposed laterally at a major surface of a semiconductor substrate; and a current path for the semiconductor controlled rectifier may be separate from a current path for the diode.

Electrostatic discharge protection device

A semiconductor device () comprising: a substrate () having a first surface (); an n-type well () extending from the first surface () into the substrate () and configured to form a depletion region () in the substrate () around the n-type well (); an insulating layer () extending over the first surface () of the substrate () from the n-type well (), the insulating layer () configured to form an inversion layer () in the substrate () extending from the n-type well () adjacent to the first surface (); wherein a p-type floating channel stopper () is provided, configured to extend through the inversion layer () to reduce electrical coupling between the n-type well () and at least part of the inversion layer (), and is electrically disconnected from a remainder of the substrate () outside of the depletion region ().

An ESD protection circuit comprises a series connection of at least two protection components between a signal line to be protected and a return line (e.g. ground), comprising a first protection component connected to the signal line and a second protection component connected to the ground line. They are connected with opposite polarity so that when one conducts in forward direction the other conducts in reverse breakdown mode. A bias voltage source connects to the junction between the two protection components through a bias impedance. The use of the bias voltage enables the signal distortions resulting from the ESD protection circuit to be reduced.

ESD protection

Circuit protection is provided. In accordance with one or more example embodiments, a thyristor-based circuit and a diode-based circuit are connected in series between an internal circuit terminal and reference terminal, for protecting the internal circuit terminal against circuit stresses such as overvoltage and/or overcurrent, as may be associated with electrostatic discharge. The thyristor and diode-based circuits operate in a first mode at which leakage current is limited by the thyristor, and in a second (protection) mode in which a voltage at the internal terminal exceeds a threshold level at which the thyristor-based circuit operates in a forward-biased mode and the diode operates in a breakdown mode, for shunting current between the internal circuit terminal and reference terminal.

Protection circuit

An integrated circuit device provides electrostatic discharge (ESD) protection. In connection with various example embodiments, an ESD protection circuit includes a diode-type circuit having a p-n junction that exhibits a low breakdown voltage. Connected in series with the diode between an internal node susceptible to an ESD pulse and ground, are regions of opposite polarity having junctions therebetween for mitigating the passage of leakage current via voltage sharing with the diode's junction. Upon reaching the breakdown voltage, the diode shunts current to ground via another substrate region, bypassing one or more junctions of the regions of opposite polarity and facilitating a low clamping voltage.

Growing community of inventors

Hamburg, Germany

Hans-Martin Ritter