Hiroshima University

Semiconductor Technology Academic Research Center

Hans Jurgen Mattausch

Tetsushi Koide

Takashi Morimoto

Youmei Harada

Tetsuo Hironaka

Koh Johguchi

Hiroshi Uchida

Zhaomin Zhu

Yuji Yano

Koji Kishi

Nobuhiko Omori

Takayuki Gyoten

Yoshinori Shirakawa

Masahiro Mizokami

The present invention is directed to a pattern recognition system in which new reference data to be added is efficiently learned. In the pattern recognition system, there is performed the calculation of distances equivalent to similarities between input data of a pattern search target and a plurality of reference data, and based on input data of a fixed number of times corresponding to the reference data set as a recognized winner, a gravity center thereof is calculated to optimize the reference data. Furthermore, a threshold value is changed to enlarge/reduce recognition areas, whereby erroneous recognition is prevented and a recognition rate is improved.

Reference data optimization learning method and pattern recognition system

In a boundary active only scheme proposed by the present invention, only a cell in a boundary of region growth is brought into an active mode, and the other cells are brought into a standby mode. The respective cells perform state transition in parallel, and decision of the state transition performed for each clock cycle is not performed in a case where any of the three conditions that none of the adjacent cells is ignited, the cell itself is already ignited, and the cell already belongs to a certain divided region is satisfied. Therefore the number of simultaneously operating cells and that of coupling weight registers are minimized, and control is automatically executed to reduce power consumption.

Image segmentation apparatus, image segmentation method, and image segmentation integrated circuit for processing an image

In an associative memory, when a reference data having the minimum distance with respect to an input data is detected as winner, it is determined whether or not a distance between the input data and winner is less than a threshold value. If the distance is less than the threshold value, it is determined that the reference data detected as winner matches with the input data, and then, a rank of the reference data is improved. If the distance is more than the threshold value, it is determined that the reference data is data different from the input data, and then, the input data is written as new reference data to the associative memory and replaces the reference data with the lowest rank. The upper positions of rank form as a long-term memory, and the lower positions thereof form as a short-term memory.

Reference data recognition and learning method and pattern recognition system

Image segmentation apparatus, image segmentation method, and image segmentation integrated circuit with low power consumption for large-scale images

In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal. An access conflict management circuit receives the address signals from the registers and buffers and generates the port block signal when an access conflict to the bank occurs. A switching network receives the read/write signal and the address signal from the registers/buffers and generates a bank selection signal when no port block signal is received, so as to activate the selected bank. Thus, memory access cycle time is shortened. A synchronous 1-port bank memory is also constructed similarly.

Memory with synchronous bank architecture

In the present invention, focusing on the point that the number of transistors can be reduced to about &#x2156; of that in a prior art due to an absolute-value-of-difference calculating circuit for an associative memory being configured of an addition circuit and a bit inversion circuit. The absolute-value-of-difference calculating circuit is built in a fully-parallel type associative memory as a unit comparison circuit, and all of the outputs of the absolute-value-of-difference calculating circuits for which the number of comparisons thereof are prepared are input to weight comparison circuits, whereby the calculation of the Manhattan distance between the search data and the reference data is carried out. In accordance with the configuration, because a Manhattan distance calculating circuit can be realized by a fewer number of transistors and with a small area, an associative memory apparatus as well can be realized at a low power consumption and with a small area.

Associative memory apparatus for searching data in which manhattan distance is minimum

The conventional multi-port cache memory, which is formed by using multi-port cells, is excellent in its operating speed. However, the integration area of the constituent multi-port cells is increased in proportion to the square of the number of ports. Thus, if it is intended to decrease the cache miss probability by increasing the storage capacity, the chip size is increased correspondingly, which increases the manufacturing cost. On the other hand, the multi-port cache memory of the present invention is formed by using, as constituents, one-port cell blocks adapted for a large storage capacity, making it possible to easily provide a multi-port cache memory of a large storage capacity and reduced integration area, which has a large random access bandwidth, is capable of parallel access from a plurality of ports, and is adapted for use in advanced microprocessors having a small cache miss probability.

Multi-port cache memory

An associative memory composed of plural chips or a single chip which is preferably used in the fields of bandwidth compression for video images in mobile communication terminals and artificial intelligence systems. The associative memory is a small-area associative memory formed using CMOS technology with a fast parallel minimum-distance-search capability. The transistor number of the provided search circuit is only linear proportional to the number of rows of the associative memory. Therefore, the increase in the number of required circuits is small even if the unit number of the input data or the unit number of the reference data is large. With the associative memory, it is possible to realize the functions of video signal compression and object recognition necessary for artificial intelligence systems, data bank systems and mobile network terminals with a single chip or plural chips.

Growing community of inventors

Higashihiroshima, Japan

Hans Jurgen Mattausch