Siemens Aktiengesellschaft

Hans-Joerg Pfleiderer

Karl Knauer

Heiner Herbst

Hans-Peter Grassl

Bedrich J Hosticka

Roland Klinke

Doris Schmitt-Landsiedel

Hans-Juergen Mattausch

Gerd Neuendorf

Maria Wurm

Bernhard Hoppe

Karl-Ulrich Stein

Rudolf Koch

Max Schlichte

Juergen Pandel

Michael Koubek

Ulrich Ramacher

Alfred Schuetz

Hans-Martin Christiansen

Heiner Klar

Gerhard Grassl

A digital neural network has a plurality of neurons (NR) completely meshed with one another, each of which comprises an evaluation stage having a plurality of evaluators (B) that is equal in number to the plurality of neurons (NR) and each of which comprises a decision stage having a decision unit (E). An adjustment information (INF.sub.E) that effects a defined pre-adjustment of the decision unit (E) can be supplied to every decision unit (E) by a pre-processing means via an information input. A weighting information (INF.sub.G) can be supplied to every evaluator (B) by a pre-processing means via an individual information input. An output information (INF.sub.A) can be output by every decision unit (E) to a post-processing means via a respective individual information output. The information outputs of the decision units (E) are each connected to an individual processing input of all evaluators (B) allocated to the appertaining decision unit (E). Individual processing outputs of the evaluators (B) are connected to individual processing inputs of the decision unit (E) in the appertaining neuron (N), so that every output information (INF.sub.A) can be indirectly fed back onto every neuron (NR).

Digital neural network executed in integrated circuit technology

A static memory is constructed in a plurality of hierarchy levels. Beneficial realization possibilities are set forth with respect to the surface utilization for the drive and read-out circuits in the second hierarchy level which are especially critical. Memory cells that supply a strong cell signal are advantageously utilized so that a low expense is needed in the read circuit. By displacing periphery circuits into higher hierarchy levels, a short access time and a reduced surface requirement arise.

Hierarchically constructed memory having static memory cells

Memory cells are disclosed that avoid the utilization of analog circuits in the memory peripheral circuits when they are utilized in static memory modules and that intended to enhance the disturbed reliability when confronted by technology modifications and parameter fluctuations. Write-in thereby occurs from a write data line via a write selection transistor and read-out occurs via a read selection transistor onto a read data line. A second inverter formed of two field effect transistors serves as a feedback element in order to statically maintain the cell information. Due to an implemented asymmetry in the dimensioning between the first and second inverters, the memory cell is significantly less susceptible to information loss upon read-out when compared to a heretofore known memory cell. A precharging of the read data line is not required with these memory cells.

Static memory cell

A differential amplifier having externally controllable power consumption. The differential amplifier has an external circuit stage for signal-dependent setting of the power consumption. The circuit stage is composed of two field effect transistors connected parallel to one another that are arranged in series with a resistor of the output side via which the current source of the differential amplifier is set. The field effect transistors are driven by a level-converting circuit proceeding from the amplifier input, this level-converting circuit being equipped with a control circuit. The control circuit defines the operating points of the field effect transistors with and without applied input signal and thus controls the signal-dependent boosting of the amplifier current.

Differential amplifier having externally controllable power consumption

A differential amplifier having externally controllable power consumption. Differential amplifiers have a 'static-bias' stage for setting the quiescent currents that flow in parallel circuit branches. Two field effect transistors that are connected parallel to one another are in series with an output resistor of this stage, these field effect transistors being driven via a level-converting circuit given the appearance of an input signal to be amplified, such that a voltage boost occurs at the output resistor. This voltage boost leads to a current boost in the differential amplifier. Good driver properties, a distortion-free signal transmission and a low dissipated power are provided by this external control of the two field effect transistors that results from the amplifier inputs.

The differential amplifier has two n-channel or p-channel field effect transistors serving as controllable current sources which supply auxiliary currents upon appearance of an input signal which amplify the quiescent current. The inputs of the differential amplifier are connected to the gate terminals of the n-channel or p-channel field effect transistors via a level-converting circuit for converting the d.c. component of the input signal superimposed on a gate bias voltage to a lower or, respectively, higher output level. As a result of the control of the current sources proceeding from the amplifier input good driver qualities, a distortion-free signal transmission and a lower dissipation power are guaranteed.

Differential amplifier having controllable power consumption

An integrated circuit in complementary circuit technology comprising two field effect transistors (T1, T2) of different channel types with the first one (T2) mounted in a doped semiconductor body (1) having a first conductivity type and the other FET (T1) mounted in a semiconductor zone 2 of a second conductivity type which is arranged in said body. The object is to provide a protection against thermal overloads which can appear due to 'latch up' influences when overvoltages at the one connecting region of the field effect transistor (T1) mounted in the semiconductor zone occur. This is accomplished by the mounting of a metal contact (12) on the surface of a semiconductor region (2') inserted into the semiconductor body 1 and doped oppositely thereto with such metal contact forming a Schottky diode (D) with the semiconductor region (2') which can be connected to the connecting region of the field effect transistor T1 mounted in the semiconductor region 2 whereas the semiconductor region (2') is electrically connected to the supply voltage (V.sub.DD). The circuits are applied in CMOS circuits.

Integrated circuit in complementary circuit technology

A transversal filter has an analog shift register exhibiting a series input and a plurality of parallel outputs which are connected to a summing and/or subtracting circuit. A simple realization of signal weighting circuits assigned to the stages of the shift register is achieved in that n signal weighting devices assigned to a group of n stages are disposed in a signal path which extends from the input of the first stage of the group over all stages thereof and in that the signal weighting devices of the n stages respectively weight according to filter coefficients b.sub.1 -b.sub.n which occur in the system function

Transversal filter having an analog shift register

A transversal filter with an analog shift register has a plurality of parallel inputs and a serial output at which a filtered signal appears. An object is to provide as simple as possible a realization of the n signal evaluators allocated to the n stages of the shift register. This is achieved by providing the n signal evaluators in a signal path proceeding from the input of the first stage over all n stages, and to evaluate according to evaluation factors b.sub.n through b.sub.1 which occur in the system function

Transversal filter having parallel inputs

A function check of a programmable logic array is performed in which input lines, product term lines and ground lines are combined into an AND plane and output lines, product term lines and ground lines are combined into an OR plane. The aim is a simple method of function check which permits any potentially-existing fault to be detected. The check is achieved by generating, with a test data generator, bit patterns and applying the same to the input lines, and, through the use of a shift register, successively sensitizing the product term lines either individually or in groups, i.e. disconnecting the same from ground potential. The bit patterns occurring at the output lines are supplied to a test data evaluator. The area of use is in logic circuitry of data processing technology.

Method and arrangement for an operational check of a programmable logic

A two-dimensional image sensor integrated on a semiconductor substrate has a plurality of sensor elements disposed in rows and columns. The sensors in each row and column are individually selected in succession via parallel outputs of a vertical shift register for readout of the sensor elements. Regulation of the integration time during which charge carriers collect in the sensor elements due to incident light is achieved by selecting the sensor elements in each even-numbered row for readout a further number of times after an initial readout of the charges optically generated therein, and within the time span during which transfer of the charges from the sensor elements of the next odd-numbered rows to the column lines takes place. The further selections eliminate charges formed in the interim in a particular row. The next readout of the particular row is undertaken with an integration time for the sensor elements therein which is variably shortened by the duration of the readout for (2N-1) rows, where N is the number of even or odd numbered rows.

Two-dimensional semiconductor image sensor with regulated integration

A circuit for sensor controlled distance measurement is disclosed having two linear image sensors which are positioned to receive corresponding lines of two images derived from an object. The sensor signals are subjected to correlation measurements from which the distance of the object is determined. In the case of circuits of this sort, one endeavors to attain as exact and unfalsified a distance measurement as possible. For this purpose, the sensor signals are digitalized in evaluators, then read via transfer transistors into shift registers which undertake relative position displacements of the sensor signals in a longitudinal direction of the image sensors between individual signal cycles, and are subject to a correlation measurement. The circuit distinguishes itself in that the digital evaluation proceeds completely independently of parameters of the shift register and is thus carried out very precisely. Applications include photographic and electronic cameras.

Circuit for the sensor controlled distance measurement

A circuit for sensor-controlled telemetry has two linear image sensors each having a number of opto-electronic sensor elements on which are projected sections of corresponding lines of two separately-obtained images from an object whose range is to be determined and has a single-input evaluator post connected to each sensor element through switching transistors, which evaluators are switchable between two logic states dependent upon whether a voltage generated by accumulated charge in a sensor element is above or below a reference potential. The digitalized signals from each evaluator are serially transmitted through respective associated shift registers to a logic circuit which compares the contents of stages of shift registers for each image sensor for determining coincidence of the digital signals. The number of coincidences indicate the relative position correlation of the images on the image sensors and this number of coincidences is serially transmitted to another shift register to a counter for determination of a maximum correlation and subsequent generation of an operational range-indicating or range-finding signal.

Circuit for sensor-controlled telemetry

Video signals are stored on a continuously movable magnetic tape with a dissection of the video signals into a plurality of partial signals and simultaneously recording the partial signals in a plurality of longitudinal tracks which extend parallel to one another. Inasmuch as mutual influences of the individual image formation to be stored are to be reduced, even given a great recording density, the signal lines of the video signal are employed as partial signals, whereby the line signals belonging to a television image are combined to at least one group and are successively recorded in groups. All line signals belonging to one and the same group are simultaneously recorded on a plurality of longitudinal tracks after an intermediate storage. The invention finds particular application in video recorders having longitudinal track recording.

Method and a circuit arrangement for the storage of video signals

An integrated circuit for transferring complementary charge packets between a first and second charge transfer device has a resettable gate common to both charge transfer devices which serves as a transfer electrode for the first charge transfer device and as an electrode in the input stage of the second charge transfer device. An electrode which is maintained at a constant voltage is disposed in the second charge transfer device between the common electrode and an oppositely doped semiconductor region which is connected to a normally constant voltage which periodically is substantially reduced, thereby flooding the region beneath the common electrode with charge carriers. When the voltage connected to the oppositely doped semiconductor region is returned to a high value, a potential well is created beneath the constant voltage electrode which becomes filled with a first charge packet. Upon the appearance of the charge packet in the first transfer device beneath the common electrode, a voltage drop occurs which results in a corresponding potential drop beneath the common gate in the second charge transfer device resulting in a flow of charge carriers in reverse to the previous flow leaving a charge packet beneath the common gate which is complementary to the charge packet introduced into the first charge transfer device.

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Zorneding, Germany

Hans-Joerg Pfleiderer