Forschungsverbund Berlin E.v.

Ferdinand-Braun-Institut Ggmbh, Leibniz-Institut Fur Höchstfrequenztechnik

Hans-Joachim Wuerfl

Oliver Hilt

Konstantin Osipov

The present invention relates to a gate structure and a method for its production. In particular, the present invention relates to agate structuring of a field effect transistor (FET), wherein the field effect transistor with the same active layer can be constructed as a depletion type, or D-type, as an enhancement type, or E-type, and as a low noise type, or LN-type, on a shared substrate base using a uniform method. The gate structure according to the invention comprises a substrate; a piezoelectric active layer () disposed on the substrate (); a passivation layer () disposed on the active layer (), wherein the passivation layer () has a recess () that extends through the entire passivation layer () in the direction of the active layer (); a contact element () disposed within the recess (), wherein the contact element () extends from the active layer () to above the passivation layer (); and a cover layer () that covers the contact element () above the passivation layer (); wherein at least one layer disposed above the active layer is tensile stressed or compressively stressed in the area around the contact element, with a normal tension of |σ|>200 MPa, wherein via the individual stresses in the area around the contact element, a resulting force on the boundary area between the passivation layer and the active layer is set, which influences via the piezoelectric effect the electron density in the active layer in the area below the contact element.

Transistor and method of fabrication of the same including a gate contact formed in a recess through the passivation dielectric layer in contact with the active layer

The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode (), a plurality of source fields () and a plurality of drain fields (). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field () and/or a drain contact field (). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate. The method according to the invention for producing a transistor comprises the following steps: providing a substrate; forming a plurality of transistor cells on the substrate, each of which comprises a control electrode, a plurality of source fields and a plurality of drain fields; conductively connecting the control electrodes to each other; forming a source contact field and/or a drain contact field in each transistor cell; conductively connecting the source contact fields of each transistor cell to a source contact field; conductively connecting the drain fields of each transistor cell to a drain contact field; forming at least one bump () on each of the source contact fields and on each of the drain contact fields; providing a circuit board; conductively connecting the bumps of the source contact fields to each other by means of conductive tracks on the circuit board; and conductively connecting the bumps of the drain contact fields to each other by means of conductive tracks on the circuit board. The arrangement of the bumps and the conductive tracks on the circuit board makes a low semiconductor surface assignment by wiring possible. The arrangement according to the invention of the source fields, drain fields and control electrodes relative to the bumps makes a low heat resistance possible between the active transistor regions and the bumps.

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Zeuthen, Germany

Hans-Joachim Wuerfl