Applied Materials, Inc.

Lucent Technologies Inc.

Varian Semiconductor Equipment Associates, Inc.

Agere Systems Guardian Corp.

At+t Corp.

At&t Bell Laboratories

Agere Systems Inc.

Hans-Joachim Ludwig Gossmann

Benjamin Colombeau

Wei Zou

Qintao Zhang

Thi-Hong-Ha Vuong

Supakit Charnvanichborikarn

David James Eaglesham

Naomi Yoshida

Conor S Rafferty

Shiyu Sun

Matthias Bauer

Stanislav S Todorov

John Milo Poate

Venkataramana R Chavva

Wei Zhao

Peter Adriaan Stolk

Anthony Renau

Hiroyuki Ito

Ran-Hong Yan

Aseem Kumar Srivastava

Andrew Michael Waite

Samphy Hong

Leonard C Feldman

Joze Bevk

Tony E Haynes

David Anthony Muller

William R Bogiages, Jr

Nilay A Pradhan

Henry S Luftman

Dennis Rodier

Richard White

Paul H Citrin

Alexander K Eidukonis

Cao-Minh Vincent Lu

Ana Cristina Gomez Herrero

Ramki Kalyanaraman

Maria Lourdes Pelaz-Montes

Vincent C Venezia

Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

Horizontal GAA nano-wire and nano-slab transistors

A method of processing a semiconductor substrate, including performing a first ion implantation process on the substrate, wherein a first ion beam formed of an ionized first dopant species is directed at a top surface of the substrate and is blocked from a first portion of the substrate while being allowed to implant a second portion of the substrate, and performing a second ion implantation process on the substrate, wherein a second ion beam formed of an ionized second dopant species is directed at the top surface of the substrate and is blocked from the first portion of the substrate while being allowed to implant the second portion of the substrate, wherein an effect of the second ion implantation process on an oxidation rate of the second portion counteracts an effect of the first ion implantation process on the oxidation rate of the second portion.

Method for precision oxidation control by ion implantation

A method of operating a beamline ion implanter may include performing, in an ion implanter, a first implant procedure to implant a dopant of a first polarity into a given semiconductor substrate, and generating an estimated implant dose of the dopant of the first polarity based upon a set of filtered information, generated by the first implant procedure. The method may also include calculating an actual implant dose of the dopant of the first polarity using a predictive model based upon the estimated implant dose, and performing, in the ion implanter, an adjusted second implant procedure to implant a dopant of a second polarity into a select semiconductor substrate, based upon the actual implant dose.

Method and apparatus for controlled ion implantation

A system and method for creating various dopant concentration profiles using a single implant energy is disclosed. A plurality of implants are performed at the same implant energy but different tilt angles to implant ions at a variety of depths. The result of these implants may be a rectangular profile or a gradient profile. The resulting dopant concentration profile depends on the selection of tilt angles, doses and the number of implants. Varying tilt angle rather than varying implant energy to achieve implants of different depths may significantly improve efficiency and throughput, as the tilt angle can be changed faster than the implant energy can be changed. Additionally, this method may be performed by a number of different semiconductor processing apparatus.

System and technique for creating implanted regions using multiple tilt angles

Provided herein are approaches for forming an image sensor with increased well depth due to cryogenic ion channeling of ultra-high energy (UHE) ions. In some embodiments, a method may include providing a wafer of a semiconductor device, the semiconductor device including a photoelectric conversion region, and cooling the wafer to a temperature less than &#x2212;50&#xb0; C. The method may further include performing an ion implant to the photoelectric conversion region to form a photodiode well after cooling the wafer.

Techniques to increase CMOS image sensor well depth by cyrogenic ion channeling of ultra high energy ions

Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.

Channeled implants for SiC MOSFET fabrication

A method of performing an ion implantation process using a beam-line ion implanter, including disposing a substrate on a platen, analyzing the substrate using metrology components, communicating data relating to the analysis of the substrate to a feedforward controller, processing the data using a predictive model executed by the feedforward controller to compensate for variations in the substrate and to compensate for variations in components of the beam-line ion implanter based on historical data collected from previous implantation operations, and using output from the predictive model to adjust operational parameters of the beam-line ion implanter.

System and method for hi-precision ion implantation

Disclosed herein are methods for reducing MOSFET trench sidewall surface roughness. In some embodiments, a method includes providing a device structure including a well formed in an epitaxial layer, forming a plurality of trenches through the well and the epitaxial layer, and implanting the device structure to form a treated layer along a sidewall of just an upper portion of the device structure within each of the plurality of trenches. The method may further include etching the device structure to remove the treated layer.

Angled ion implant to reduce MOSFET trench sidewall roughness

A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.

Forming non-line-of-sight source drain extension in an NMOS FINFET using n-doped selective epitaxial growth

A method of forming an asymmetrical three dimensional semiconductor device. The method may include providing a fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the fin structure comprises a first end surface not covered by the gate structure and second end surface not covered by the gate structure. The method may further include directing ions in a fin treatment to the fin structure, wherein the fin treatment comprises a first treatment of the first end surface and a second treatment of the second end surface different from the first treatment.

Method for fabricating asymmetrical three dimensional device

Forming non-line-of-sight source drain extension in an nMOS finFET using n-doped selective epitaxial growth

A method for forming a three dimensional device. The method may include directing ions to an end surface of an extension region of a fin structure, the fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein the ions have trajectories extending in a plane perpendicular to the substrate plane and parallel to the fin axis, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the end surface is not covered by the gate structure.

Method for fabricating three dimensional device

A method of processing a workpiece to create a doped fin structure is disclosed. A portion of the workpiece is subjected to a pre-amorphizing implant to create an amorphized region. This amorphized region is then implanted with dopant species, at an implant energy and dose so that the dopant species are contained within the amorphized region. The doped amorphized region is then subjected to a laser melt anneal which crystallizes the amorphized region. The dopant profile is box-like, and the dopant is confined to the previously amorphized region.

Method for improving fin isolation

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Summit, NJ, United States of America

Hans-Joachim Ludwig Gossmann