Fraunhofer-gesellschaft Zur Foerderung Der Angewandten Forschung E.v.

University of Utah Research Foundation

Pac Tech - Packaging Technologies Gmbh

Other

Huawei Technologies Duesseldorf Gmbh

Smart Pac Gmbh Technology Services

Hans-Hermann Oppermann

Ghassem Azdasht

Elke Zakel

Kai Zoschke

Tolga Tekin

Charles-Alix Manier

Paul Kasulke

Matthias Klein

Florian Solzbacher

Richard A Normann

Rolf Aschenbrenner

Michael Töpper

Reid R Harrison

Lothar Dietrich

Martin Wilke

Michael Toepper

Juergen Wolf

Robert Gernhardt

Sohee Kim

Jörg Stockmeyer

Klaus Buschick

Juliane Fröhlich

Lena Goullon

A method for manufacturing a device is provided. The method comprises providing a first carrier having attached thereto a plurality of chips by means of an adhesive layer of the first carrier, a first surface of the plurality of chips being attached to the first carrier. Further, the method comprises selectively attaching a second surface of a subset of the plurality of chips to a conveyor carrier by means of a structured adhesive layer of the conveyor layer. Further, the method comprises selectively releasing the subset of the plurality of chips from the first carrier by means of debonding corresponding sections of the adhesive layer of the first carrier. Further, the method comprises attaching the first surface of the subset of the plurality of chips to a substrate of the device.

Massive parallel assembly method

Disclosed herein is an optical system, comprising a first optical component, featuring a first waveguide and a recess which passes at least partially through the first optical component from a front side to a back side, a second optical component, arranged in the recess of the first optical component, and a second waveguide optically coupled with the first waveguide, and a carrier substrate. The first optical component including a first marking set with a defined position/orientation relative to the first waveguide, the second optical component including a second marking set with a defined position/orientation relative to the second waveguide, and based on a relative position/orientation of the first and second marking sets, determine whether the first and the second optical components are aligned in a reference plane that is parallel to a surface of the carrier substrate, such that the first and the second waveguide are optically coupled.

Optical system, optical components, and method for manufacturing an optical system

An assembly may include at least one camera and a controllable mechanical handling device. The system may further include a first component, including a first optical waveguide and a second component, including a second optical waveguide. The first component and the second component are fixedly connected to a substrate and arranged directly next to one another on the substrate and relative to one another in such a way that a coupling side of the first component and a coupling side of the second component are situated opposite each other on a first and second side of a coupling plane. The optical waveguides of the first and second component each end at a first coupling surface or a second coupling surface. The first and second coupling sides are aligned, and optically coupled with one another at a first and second end face.

Assembly comprising a substrate and two components including optical waveguides, as well as method for production

Disclosed is a system for and a method of manufacturing of an optical system, including a first optical component, comprising a first waveguide and a carrier substrate, wherein the first optical component is arranged on the carrier substrate. The first optical component comprises a first markup set having a defined position/orientation with respect to the first waveguide, the carrier substrate has a second markup set detectable based on a relative position/orientation of the first and second markup sets when a desired orientation of the first waveguide relative to the carrier substrate is achieved in a reference plane extending parallel to a surface of the carrier substrate.

Markup system for optical system, carrier substrate, and method for manufacturing of same

A method for manufacturing a semiconductor component including: providing a flat carrier with an upper side and a lower side, the carrier including a continuous opening that runs between the upper side and the lower side; providing a semiconductor arrangement that includes a semiconductor chip that includes electrically and/or optically active regions on a lower side; arranging the semiconductor arrangement in the opening such that a lower side of the semiconductor arrangement and the lower side of the carrier run in a common plane; casting the semiconductor arrangement with a potting compound, such that the semiconductor arrangement is materially connected to the carrier; and thinning out the semiconductor system by way of grinding from above, such that an upper side of the carrier and an upper side of the semiconductor arrangement run in a common plane.

Method for manufacturing a semiconductor component and a semiconductor component

A method for arranging electronic components that includes a plurality of electronic components pasted onto a first front face of a carrier having a bonding layer. The front face and/or the electronic components being provided with a plurality of bonding points and the diameter of and distance between the bonding points are selected such that each of the plurality of electronic components is attached by at least three bonding points to the carrier having the bonding layer. The method also includes arranging at least one portion of the plurality of the components on a switching element carrier and connecting the components to the carrier. The method also includes detaching a component from the carrier having a bonding layer, using a solvent or a mechanical force that separates the carrier having a bonding layer and the switching element carrier from one another.

Method for arranging electronic switching elements, electronic switching arrangement and use of a carrier having a bonding layer

An arrangement of a substrate with at least one optical waveguide and with an optical coupling location for coupling in and/or coupling out an optical a radiation into and/or out of the at least one optical waveguide, and of at least one optoelectronic component which is assembled on the substrate and a method for manufacturing such an arrangement is suggested. The optical coupling location is designed in a manner such that the radiation is coupled in and/or coupled out with a coupling-in and/or coupling-out angle of greater than 2&#xb0; to the perpendicular to the substrate surface. The optoelectronic component is assembled over the coupling location on the substrate in a manner tilted obliquely to the substrate surface, wherein the tilt angle to this surface corresponds to the coupling-in angle and/or coupling out-angle.

Arrangement of a substrate with at least one optical waveguide and with an optical coupling location and of an optoelectronic component, and method for manufacturing such an arrangement

An optical coupling system having an optical coupler and a light-transmissive external medium, the optical coupler comprising a light guide which extends parallel to a main plane of the optical coupler, a mirror surface which is inclined relative to the main plane by an angle of inclination and an outer surface of the coupler which abuts on the medium, the waveguide.

Optical coupling system having an optical coupler and a light-transmissive external medium and also production and use of such a system

The invention relates to a component arrangement with a first substrate and at least one second substrate arranged on the first substrate, wherein the first substrate has at least one first contact element and the at least one second substrate has at least one second contact element and the contact elements each has a contact surface connected such as to give an electrical contact and a protective layer connecting the first and second substrate together. During production the protective layer is structured such that a part surface of the first substrate and a part surface of the at least one second substrate are not covered, wherein the part surfaces include the contact surfaces of the at least one first and second contact elements and the contact generated between the contact surfaces is hence not contaminated by the protective layer. The contact surfaces are thus freely accessible without elements of the protective layer lying therebetween. An improved electrical conductivity with constant mechanical stability is thus generated.

Component arrangement and method for production thereof

An in-vivo implantable coil assembly includes a planar coil having at least one coil layer formed from conductive traces disposed in or on a polymer matrix. A ferrite platelet is bonded to a surface of the polymer matrix. Methods of making and using the in-vivo implantable coil assembly are also disclosed.

In vivo implantable coil assembly

A method is provided for the production of a bond between a first element having at least one first metal coating and at least one further element having a second metal coating, the at least one further element being freely moveable in a medium and the at least one first metal coating of the first element and the second metal coating of the at least one further element being in a solid state, a liquid phase being formed upon contact of the at least one first metal coating with the second metal coating.

Self-assembly of components

Interconnect metallization schemes and devices for flip chip bonding are disclosed and described. Metallization schemes include an adhesion layer, a diffusion barrier layer, a wetable layer, and a wetting stop layer. Various thicknesses and materials for use in the different layers are disclosed and are particularly useful for metallization in implantable electronic devices such as neural electrode arrays.

Flip chip metallization method and devices

Process for the formation of a spatial chip arrangement having several chips () arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces () to assigned conducting paths () of a conducting-path structure () arranged on at least one carrier substrate () by the chips being arranged transverse to the longitudinal extent of the carrier substrate.

Process for the formation of a spatial chip arrangement and spatial chip arrangement

An electronic contacting method for contacting a chip having a plurality of conductive contact areas, which are not provided with an additional metallization layer, a carrier substrate is provided, which has a first surface having arranged thereon a plurality of conductive connecting sections. A non-conductive adhesive layer is arranged on the first surface of the carrier substrate and subsequently, the carrier substrate is aligned with a chip to be contacted in such away that a plurality of conductive contact areas on said chip to be contacted is in alignment with the connecting sections on the first surface of said carrier substrate. Then the carrier substrate is connected to the chip to be contacted by means of the adhesive layer in such a way that the connecting sections of the carrier substrate and the contact areas of the chip abut on one another by means of pressure contact, without any intermetallic connection being established.

Contact-bumpless chip contacting method and an electronic circuit produced by said method

Process for the formation of a spatial chip arrangement having several chips (,) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces (,) to assigned conducting paths (,) of a conducting-path structure (,) arranged on at least one carrier substrate (,) by the chips being arranged either transverse to the longitudinal extent of the carrier substrate or parallel to the longitudinal extent of the flexibly constructed carrier substrate, as well as a spatial chip arrangement that is formed by means of this process.

Growing community of inventors

Berlin, Germany

Hans-Hermann Oppermann