Infineon Technologies Ag

International Business Machines Corporation

Qimonda Ag

Infineon Technologies North America Corp.

Hans-Heinrich Viehmann

Stefan Lammers

Dietmar Gogl

Oliver Kiehl

John Kenneth DeBrosse

Thomas M Maffitt

Christian Peters

Uwe Weder

Christoph Braun

Dirk Uffmann

John E Barwin

A power amplifier is disclosed. In one embodiment, the power amplifier is a Class-D Amplifier having a differential pulse width modulator is disclosed. The differential pulse width modulator has an input for receiving an input signal, a first output for outputting a first signal and a second output for outputting a second signal. A difference between the first signal and the second signal represents the pulse modulated signal. The differential pulse width modulator further has a comparator for comparing the first and second output signals. The comparator switches both the first and second output signal from a high state to a low state, if both the first and second output signals are in a high state.

Power amplifier

An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.

Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module

A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal node. The first clamping device is coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal node. The second clamping device is also coupled to the reference voltage. A current mirror is coupled between the first and second input of the voltage comparator and is coupled to an active capacitance balancing circuit. The active capacitance balancing circuit may be combined with the voltage comparator. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal node and the second input signal node.

Current sense amplifier

A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.

Sense amplifier bitline boost circuit

The write path of an MRAM device is precharged before starting a write operation of a magnetic memory cell, increasing the speed of the write operation and decreasing the write cycle time. The reference wires are precharged, which provides better control over the wordline and bitline write pulses and results in shorter rise times. The precharge time can be hidden in the address decoding time or redundancy evaluation time. A circuit design for a global reference current generator is also described herein. A fast on circuit is also disclosed that increases the speed of precharging the reference wires.

Precharging the write path of an MRAM device for fast write operation

An integrated circuit includes at least one main circuitoperable to perform one or more functions. At least one termination node DQ receives or transmits an operating signal. An active termination circuithas first and second transistors of opposite type coupled in series between a Vdd node of a first source potential and a Vss node of a second source potential. The at least one termination node is coupled to a common node between the first and second transistors. A control circuit operates to bias the first and second transistors such that they exhibit a controlled impedance at the common node. Alternatively, the control circuit operates to bias the first and second transistors such that they provide a clamping function at the common node.

Methods and apparatus for active termination of high-frequency signals

An integrated circuit, comprising: at least one main circuit operable to perform one or more functions, and including at least one I/O node for receiving or transmitting an operating signal; an active termination circuit having first and second MOSFETs of the same type coupled in series across a Vdd node of a first source potential and a Vss node of a second source potential, the at least one I/O node being coupled to a common node between the first and second MOSFETs; and a control circuit operable to bias the first and second MOSFETs such that they exhibit a controlled impedance at the common node.

A method of storing information in a cross-point magnetic memory array and a cross-point magnetic memory device structure. The voltage drop across magnetic tunnel junctions (MTJ's) during a write operation is minimized to prevent damage to the MTJ's of the array. The voltage drop across the selected MTJ's, the unselected MTJ's, or both, is minimized during a write operation, reducing stress across the MTJ's, decreasing leakage currents, decreasing power consumption and increasing the write margin.

Cross-point MRAM array with reduced voltage drop across MTJ's

A selection device for a semiconductor memory device for preventing voltage drops caused by read currents in a column multiplexer of a semiconductor memory device includes switch devices having two switch elements. Associated bit lines can be interlinked with a potential sampling connection or a current feed connection of a respective associated sense amplifier by the first and the second switch element.

Selection device for a semiconductor memory device

An apparatus for transforming single ended signals into differential mode signals. A preferred embodiment comprises an inverter (for example, inverter) and a pair of latches (for example, latchesand). One latch has as its input an input signal to be converted and the other latch has as its input an inverse of the input signal. The latches maybe clocked by a differential mode clock and remove a timing mismatch between the input signal and its inverse that is incurred via the inverter. The latch outputs are then provided to a differential mode buffer to perform signal voltage and current compatibility transformations.

Circuit for transforming a single ended signal into a differential mode signal

An apparatus for use as both an off chip driver (OCD) and an on die termination (ODT) circuits. A preferred embodiment comprises a control circuit (for example, control circuit) coupled to a dual function OCD/ODT circuit (for example, OCD/ODT circuit) with an enable line coupled to the control circuit. The control circuit may be used to selectively choose OCD and ODT functionality based on a value on the enable line. With the control circuit choosing OCD, the dual function OCD/ODT circuit functions as an OCD circuit, placing signals provided through the control circuit onto a transmission line. With the control circuit choosing ODT, the dual function OCD/ODT circuit becomes terminating resistors for incoming signals on a transmission line. The use of a single circuit for both OCD and ODT functions can save both integrated circuit real-estate and implementation costs due to a reduction in use of circuit elements.

CML (current mode logic) OCD (off chip driver)&#x2014;ODT (on die termination) circuit for bidirectional data transmission

A memory sense amplifier for a semiconductor memory device is provided with a compensation current source device that generates a compensation current and feeds it to an interconnected bit line. The compensation current is selected in such a manner that during readout a potential gradient can be generated and/or maintained in cooperation with a compensation voltage source device on the selected and interlinked bit line device that is substantially constant over time.

Sense amplifier configuration for a semiconductor memory device

An apparatus for a current mode logic variable delay element. A preferred embodiment comprises an input signal that is provided to a multiplexer (for example, multiplexer ) in both buffered (via a buffer (for example, buffer )) and unbuffered form. A control signal of the multiplexer may be used to select from either the buffered or unbuffered input signals. By using a control signal at an intermediate value (somewhere in between values that selects the buffered or unbuffered input signals), the multiplexer may then combine the buffered and unbuffered input signals in proportion with the value of the control signal and imparts a delay upon the input signal that may be in between the delay imparted by the buffer.

Current mode logic (CML) circuit concept for a variable delay element

An apparatus for converting a differential mode signal into a single ended signal with reduced power consumption. A preferred embodiment comprises a single ended converter (for example, a single ended converter ) and an output transistor (for example, output transistor ) that when the single ended converter is in standby may pull the output of the single ended converter to a known logic state (such as high logic or low logic). A single ended buffer (inverting or non-inverting) may be used for output signal compatibility conversion.

Circuit for transforming a differential mode signal into a single ended signal with reduced standby current consumption

A description is given of a memory device having memory cells for storing data. The memory device described is distinguished by the fact that a current switch-off device is provided, which prevents an existing current flow through the memory cell to be read in response to the identification of the memory cell content, and/or that a discharge device is provided, which partly discharges again a node in the memory cell which is to be precharged before the memory cell is read.

Growing community of inventors

South Burlington, VT, United States of America

Hans-Heinrich Viehmann