Telefonaktiebolaget Lm Ericsson (publ)

Hans Hagberg

Magnus Nilsson

Sven Erik Mattisson

Peter Jakobsson

Torsten John Carlsson

Kjell Berthold Gustafsson

Martin Isberg

Bjorn Martin Lindquist

Jacob Mannerstrangle

Lars Peter Kunkel

Leif Magnus Nilsson

Leif Magnus Andre Nilsson

Viktor Arfwedson

In an Advanced Antenna System, a desired power amplifier, PA, load distribution, which counters the mismatch of active impedance load, is achieved by altering the lengths of routing traces connecting PA outputs and corresponding antenna elements/subarrays. The combined output performance in the beam during active impedance load is then restored to the matched condition performance. This can be visualized as distributing the load impedance more evenly—ideally, on a circle—on a Smith chart.

Advanced antenna system active impedance load mitigation

Disclosed are methods and circuit configurations for reference frequency signal distribution circuitry that suppress unwanted spurious components introduced by way of RF signal leakage. The methods and circuitry may include relocating components of a buffer along a reference frequency signal path, thereby suppressing conductive and inductive components associated with RF leakage paths entering the circuitry. A filter also may be used after the buffer to suppress spurious components resulting from subsampling of unwanted tones in a phase frequency detector or intermodulation between the reference signal and interference tones in the signal-path of the buffer.

XO-buffer robust to interference

A phase-locked loop includes a phase detector, a loop filter, a voltage controlled oscillator and a frequency divider arranged such that the phase detector generates a phase detector output signal as a function of a phase difference between the reference clock signal and the feedback signal; the loop filter generates a frequency control signal from the phase detector output signal; the voltage controlled oscillator generates a phase-locked loop output signal that has a frequency that is controlled by the frequency control signal; and the frequency divider generates the feedback signal from the phase-locked loop output signal. The phase-locked loop further includes one or more circuit elements that maintain an operating point of the phase detector such that, for a predetermined range of both positive and negative phase differences between the reference clock signal and the feedback signal, the output signal is generated as a substantially linear function of the phase difference between the reference clock signal and the feedback signal.

Linear dead-band-free digital phase detection

A phase-locked loop has a phase detector that generates a phase difference signal, a circuit that generates a phase-locked loop output signal having a frequency that is a function of the phase difference signal, a frequency divider that receives the phase-locked loop output signal and generates therefrom a divided frequency signal. To substantially reduce variation in the duty cycle of the divided frequency signal, a comparison signal having one half the frequency of the divided frequency signal is generated. This may be performed by configuring a latch to toggle its output state once for every cycle of the divided frequency signal. To compensate for the additional division by two in the feedback path, the phase detector may use a dual-edge triggered latch to generate the phase difference signal so that it represents a phase difference between the reference signal and a signal having twice the frequency of the comparison signal.

Fractional-N phase locked loop

The present invention helps to mitigate and reduce the amount of interfering signals (e.g. RF leakage) that enter the phase detector of a phase locked loop by acting as a less than perfect sampler. This is accomplished by introducing a time jitter to the signal edges that enter the phase detector input. A phase detector can also be made to act as a less than perfect sampler by intentionally introducing an interfering signal. For example, a small interfering analog signal can be introduced with a different frequency from the reference frequency already present in the PLL. The interfering signal will cause the stable internal signal to vary slightly in time at the rate of the interfering signal frequency. It is this signal variation and jitter introduced on the signal edges entering the phase detector input that induces the phase detector to act as a less than perfect sampler.

Generation of a phase locked loop output signal having reduced spurious spectral components

The present invention relates to a receiver device comprising a receiver (104) adapted to receive radio signals in two frequency bands (FB1, FB2). The radio signals in one of the frequency bands (FB1) constitute communication signals for a radio system (AMPS, NMT) having a certain channel spacing, whereas the radio signals of the second frequency band (FB2) constitutes communication signals for a second radio system (PCS1900, DCS1800, GSM) having a second certain channel spacing. The receiver (104) comprises two inputs (108, 11) each intended for a radio system having different frequency bands and channel spacing. For radio signals occurring on one input (108), mixing is performed from the RF range directly to the baseband frequency range. For radio signals occurring on the second input (108) the mixing from the radio frequency range to the baseband frequency range is carried out through an intermediate frequency range. Further the receiver (104) comprises an output (112) intended to deliver baseband signals for both radio systems. The output (112) is connected to a baseband unit which is common to the radio systems. In the baseband unit, among other things, lowpass filtering, detection and neighbouring channel suppression are performed on the received radio signal that has been mixed down to the baseband frequency range.

Multi-frequency band receiver for RF signal

A phase-locked loop bandwidth is tuned to a desired level by operating the phase-locked loop in a phase-locked condition at a first frequency and applying a step response to the phase-locked loop by causing the phase-locked loop to begin locking to a second frequency that is different from the first frequency. A parameter is then detected that is related to the applied step response and that is indicative of whether the phase-locked loop bandwidth is at the desired level. The phase-locked loop bandwidth is adjusted, and the steps of operating at the first frequency, applying the step response, detecting the parameter and adjusting the phase-locked loop bandwidth are repeated until the phase-locked loop bandwidth is at the desired level. Where the desired bandwidth level for tuning is not the operational bandwidth, the phase-locked loop bandwidth is further adjusted by a predetermined amount, thereby tuning the phase-locked loop bandwidth to an operational level. The step response may be applied by changing a frequency division value in a feedback path of the phase-locked loop. The detected parameter may be a pulse skip, which indicates that the bandwidth of the phase-locked loop is not yet at the desired bandwidth level.

Tuning the bandwidth of a phase-locked loop

A multi-divide frequency divider, includes a chain of serially-connected frequency divider units, each responding to a first state of received control signals by using the reference clock signal to generate an output signal having a frequency that is the reference clock frequency divided by a first divisor, and each responding to a second state of the control signals by using the reference clock signal to generate an output signal having a frequency that is the reference clock frequency divided by a second divisor. The output signal may be supplied to a successor frequency divider unit in the chain. Division by the first and second divisors causes the frequency divider to respectively transition through first and second predetermined state sequences. Each frequency divider further responds to a third state of the control signals by initializing the frequency divider to an initial state that is common to both the first and second predetermined state sequences, whereby the frequency divider in the initial state is immediately responsive to subsequent application of the first state of the control signals, and is immediately responsive to subsequent application of the second state of the control signals. Receipt of a received swallow enable control signal having a predetermined value disables division by the second divisor. Each frequency divider further generates an output control signal having the predetermined value whenever the frequency divider is in the initial state.

Growing community of inventors

Malmö, Sweden

Hans Hagberg