Avago Technologies General IP (singapore) Pte. Ltd.

Agilent Technologies, Inc.

Avago Technologies International Sales Pte. Limited

Avago Technologies Wireless IP (singapore) Pte. Ltd.

Hans G Rohdin

John H Stanback

Nicolas J Moll

Jonathan Kwadwo Abrokwah

Chung-Yi Su

Dave P Bour

John Stephen Kofol

Nathan Perkins

Domingo Figueredo

Brice Ivira

Bartholomeus Hendrik Jansen

Alexia Kekoa

Sung Soo Yi

Arlene Sachiyo Wakita-Oyama

Nate Perkins

Phil Marsh

Philbert Marsh

John Shi Sun Wei

Bulk acoustic wave (BAW) resonators, and electrical filters that incorporate the BAW resonators, are described. Generally, the BAW resonators comprise a substrate comprising an acoustic reflector; a first electrode disposed over the acoustic reflector; a piezoelectric layer disposed over the first electrode, the piezoelectric layer comprising scandium-doped aluminum nitride (ASN); a diffusion barrier layer disposed over the piezoelectric layer; and a second electrode disposed over the diffusion barrier layer. The diffusion barrier layer configured to prevent diffusion of material of the first electrode into the piezoelectric layer.

Bulk acoustic wave resonators having doped piezoelectric material and an adhesion and diffusion barrier layer

A method is provided for calibrating a device under calibration (DUC) for optimizing performance of the DUC. The method includes receiving stimulus signal characteristics of a stimulus signal to be generated by the signal generator, including modulation type and duty cycle, where the stimulus signal characteristics are within a normal operating range of the DUC; receiving average output power set points and RF carrier frequencies of a DUC output signal; outputting the stimulus signal characteristics to a signal generator for generating the stimulus signal; iteratively performing an optimization process, using DUC calibration parameters that are simultaneously adjusted between consecutive iterations of the optimization process, to determine corresponding error functions based on measured power supply currents, output powers and linearities of the DUC output signal for the consecutive iterations, respectively, until a difference between consecutive error function values reaches a specified minimum; and using values of the calibration parameters corresponding to a last iteration.

Method of calibrating electronic device for optimized overall specification-driven performance using stimuli within normal operation ranges of the electronic device

A pseudomorphic high electron mobility transistor (pHEMT) comprises: a substrate comprising a Group III-V semiconductor material; buffer layer disposed over the substrate; and a channel layer disposed over the buffer layer. The buffer layer comprises microprecipitates of a Group V semiconductor element. A method of fabricating a pHEMT is also described.

Pseudomorphic high electron mobility transistor (pHEMT) comprising low temperature buffer layer

A pseudomorphic high electron mobility transistor (PHEMT) comprises a substrate comprising a Group III-V semiconductor material, a buffer layer disposed over the substrate, wherein the buffer layer comprises microprecipitates of a Group V semiconductor element and is doped with an N-type dopant, and a channel layer disposed over the buffer layer.

Pseudomorphic high electron mobility transistor comprising doped low temperature buffer layer

An embodiment of a circuit for biasing a transistor such as an amplifier transistor includes reference and bias nodes, and includes buffer, reference, and feedback stages. The reference node receives a reference current, and the bias node, which is for coupling to the transistor, carries a bias signal. The buffer stage buffers the reference node from the bias node. The reference stage generates the bias signal from the reference current, and the bias signal causes the transistor to conduct a bias current that is proportional to the reference current. And the feedback stage is coupled between the reference and bias nodes. As compared to known bias circuits, such a bias circuit may reduce the amplitude and duration of a transient overshoot in the bias current of a field-effect transistor when the DC component of the transistor's drain voltage transitions from one value to another value. Such a bias circuit may also reduce the difference between the values of the bias current through the transistor for different supply voltages. And such a bias circuit may reduce the difference between the predicted and actual values of the bias current through the transistor for a given input voltage such as that between the gate and the source of a field-effect transistor.

Circuit for biasing a transistor and related system and method

A heterojunction for a semiconductor device. The heterojunction has a first region formed from a first semiconductor material having a first conductivity type, a second region formed from a second semiconductor material having a second conductivity type, and an intermediate layer between the first region and the second region. The band line-up of the first region, the intermediate layer, and the second region has no bound states in its conduction band and no bound states in its valence band. The intermediate layer has a thickness small enough to allow electrons to tunnel from the first region to the second region with negligible attenuation. The semiconductor device may be a heterojunction bipolar transistor. The conduction band of the intermediate layer has a higher energy level than the conduction bands of the first and second regions.

Heterojunction semiconductor device having an intermediate layer for providing an improved junction

A transistor structure with a degradation-stop layer that prevents degradation of underlying semiconductor layers while minimizing any increase in the gate leakage current is disclosed. In one embodiment, a transistor structure includes: a substrate; a channel layer formed of a charge transport material over the substrate; a Schottky barrier layer formed of an aluminum-containing material over the channel layer; a degradation-stop layer formed of a substantially aluminum-free material over the Schottky barrier layer; and a source, a drain and a gate. The source and the drain being formed over or alloyed through the degradation-stop layer, and a lower portion of the gate extends down through an exposed portion of the degradation-stop layer and is in physical and electrical contact with the Schottky barrier layer.

Sintered gate schottky barrier fet passivated by a degradation-stop layer

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Los Altos, CA, United States of America

Hans G Rohdin