Telefonaktiebolaget Lm Ericsson (publ)

K.eklund Innovation

Hans Erik Norstrom

Sam-Hyo Hong

Torbjorn Larsson

Bo Anders Lindgren

Stefan Nygren

Anders Lindgren

Andrej Litwin

Ulf Smith

Klas-Hakan Eklund

Jonas Jönsson

Ola Knut Tylstedt

Shili Zhang

A semiconductor based integrated sensor device includes: a lateral insulating-gate field effect transistor (MOSFET) connected in series to the base of a vertical bipolar junction transistor (BJT) wherein the drain-drift-region of the MOSFET is part of the base-region of the BJT within the semiconductor substrate thus making electrical contact to the base of the BJT and the distance of the drain-drift-region of the MOSFET to the emitter of the BJT exceeds the vertical distance between the emitter and any buried layer, serving as collector, and the breakdown voltage of the device being determined by the BVof the vertical BJT.

Integrated circuit sensor device for charge detection hybridizing a lateral metal oxide semiconductor field effect transistor (MOSFET) and a vertical bipolar junction transistor (BJT)

The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped ( ) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure ( ) down to a depth lower than the depth of the surrounding field oxide ( ), and that the semiconductor structure ( ) is then heat treated. The trench ( ) is achieved by uncovering a predetermined area of the upper silicon surface ( ), etching the semiconductor structure ( ) within the predetermined area to a predetermined depth, uniformly depositing a first oxide layer ( ), preferably of the type LPCVD-TEOS over the semiconductor structure, especially in the trench, uniformly depositing a barrier layer ( ), preferably of silicon nitride, over the first oxide layer ( ), filling the trench ( ) by depositing a silicon layer ( ), which is subsequently etched back, over the nitride layer ( ), especially in the trench ( ), and thermally growing a cap oxide ( ) over the trench filling ( ).

Integrated circuit components thereof and manufacturing method

Integrated circuit, components thereof and manufacturing method

A semiconductor integrated circuit comprises a substrate (,) of a first conduction type semiconductor material, an epitaxial layer (,) which is carried by the substrate (,) and which is of a second conduction type semiconductor material different to the first conduction type material, a well (,) of semiconductor material in the epitaxial layer and a semiconductor material, the epitaxial layer (,) being substantially depleted of charges is a region substantially beneath the well (,).

Integrated circuits

The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (,) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (,) down to a depth lower than the depth of the surrounding field oxide (,), and that the semiconductor structure (,) is then heat treated. The trench (,) is achieved by uncovering a predetermined area of the upper silicon surface (,), etching the semiconductor structure (,) within the predetermined area to a predetermined depth, uniformly depositing a first oxide layer (,), preferably of the type LPCVD-TEOS over the semiconductor structure, especially in the trench, uniformly depositing a barrier layer (,), preferably of silicon nitride, over the first oxide layer (,), filling the trench (,) by depositing a silicon layer (,), which is subsequently etched back, over the nitride layer (,), especially in the trench (,), and thermally growing a cap oxide (,) over the trench filling (,).

A protective circuit is disclosed for protecting an integrated circuit against electrostatic discharge, so-called ESD. The integrated circuit is connected to a supply voltage via a V.sub.cc -pad (2) and an earth pad (3). The protective circuit, which is particularly intended to protect a positively supplied circuit for radio frequency applications against both negative and positive voltage pulses, comprises an input pad (14) and at least one PNP-transistor (20), the input pad being connected to the integrated circuit, and the PNP-transistor being connected with its collector to the input pad, and its emitter to the V.sub.cc -pad or to the earth pad. The base of the PNP-transistor can be connected to its emitter either directly or via a resistor (24), or not be connected.

Protective circuit

In order to produce an electrical connection to an inner layer such as a bottom diffusion (103), which has a good electrical conductivity and is located inside a bipolar semiconductor device isolated by trenches (119) and which for example forms a subcollector of a NPN-transistor, a hole (157) in a trench is used. The hole is filled with electrically conducting material and extends from the surface of the device to the bottom diffusion (103), so that the electrically conducting material in the hole is in contact therewith. The hole (157) is made aligned with a sidewall of the trench (119) by using selective etching. The hole can be made at the same time as contact holes for metallization are made and then also be filled in the metallization step, to contact the bottom diffusion. For a lateral PNP-transistor the hole can be made as a closed groove constituting the outer confinement of the base area, passing all around the transistor. The outer sidewall of such a closed trench can, as seen from above, be bevelled by 45.degree., so that no inner corners having too small angles are found in the trench, what facilitates the filling with oxide.

Method of electrical connection through an isolation trench to form

The present invention relates to a method for, in the manufacturing of an integrated circuit, producing a capacitor with metallic conducting electrodes and to the capacitor itself and to the integrated circuit, which preferably are intended for high-frequency applications. According to the invention, a lower electrode (17,63,67) is produced through depositing a first metal layer (15) onto a layer structure (11) comprising lowermost a substrate and uppermost an insulating layer (13). An insulating layer (19) is deposited over the first metal layer (15), whereafter an electrical connection (25) to the lower electrode (17,63,67) is produced by etching a via hole (21) through the insulating layer (19), which via hole (21) is plugged. Thereafter the first metal layer (15) is uncovered within a predetermined area (33), whereafter a dielectric layer (35) is deposited, patterned and etched in such a way that it overlaps (39) a portion of the second insulating layer (19). Finally, an upper electrode (47,63,67) and a connecting layer (43) are produced through a second metal layer (41) being deposited on the structure (40) achieved thereby, which second metal layer (41) is patterned and etched in such a way that the upper electrode (47,63,67) overlaps (49) the second insulating layer (19) and the connecting layer (43) overlaps the plugged via hole (21).

Capacitors in integrated circuits

The present invention relates to a method for, in the manufacturing of an integrated circuit, producing a capacitor with metallic conducting electrodes and to the capacitor itself and to the integrated circuit, which preferably are intended for high-frequency applications. According to the invention, a lower electrode (17,63,67) is produced through depositing a first metal layer (15) onto a layer structure (11) comprising lowermost a substrate and uppermost an insulating layer (13). An insulating layer (19) is deposited over the first metal layer (15), whereafter an electrical connection (25) to the lower electrode (17,63,67) is produced by etching a via hole (21) through said insulating layer (19), which via hole (21) is plugged. There-after the first metal layer (15) is uncovered within a predetermined area (33), whereafter a dielectric layer (35) is deposited, patterned and etched in such a way that it overlaps (39) said predetermined area (33). Finally, an upper electrode (47,63,67) and a connecting layer (43) are produced through a second metal layer (41) being deposited on the structure (40) achieved thereby, which second metal layer (41) is patterned and etched in such a way that the upper electrode (47,63,67) overlaps (49) said predetermined area (33) and the connecting layer (43) overlaps the plugged via hole (21).

A method of manufacturing a bipolar transistor having a self-registered base-emitter structure is provided. The method involves the steps of: depositing a layer of amorphous silicon on a substrate of crystalline silicon having an upper region of a first conductor type; doping the amorphous silicon layer with a dopant to form a second conductor type; depositing at least one dielectric layer on the amorphous silicon layer in a manner such as to prevent crystallization of the amorphous silicon layer; patterning the resultant structure and thereafter etching away the dielectric layer and the amorphous silicon layer within a predetermined region such as to define an emitter opening; growing a thermal oxide on the resultant structure, wherein the amorphous silicon layer is converted to a polycrystalline silicon layer; forming an intrinsic base of the same conductor type as the polycrystalline layer by doping through the thermal oxide; depositing a layer of electrically insulating material on the resultant structure and thereafter etching the structure anisotropically until a thin oxide layer remains on the substrate in the emitter opening and in such a manner that a spacer of the electrically insulating material remains along the side walls of the emitter opening; removing the thin oxide layer; forming an emitter contact in the emitter opening and doping the emitter contact to the first conductor type; and heat-treating the structure to form an emitter-base junction in the substrate by out diffusion of the dopants from the emitter contact.

Growing community of inventors

Solna, Sweden

Hans Erik Norstrom