Infineon Technologies Ag

Hans-Eberhard Kr&ouml;bel

Richard Stepp

Timo Gossmann

Markus Scholz

In order to detect a received signal quickly and reliably, an integrated circuit for detecting a received signal has an intermediate frequency detector which supplies a first search run stop signal if the intermediate frequency lies within a given range. Furthermore, a field-strength comparator is provided which supplies a second search run stop signal if the field-strength of the received signal exceeds a field-strength setpoint value. In addition, a multipath comparator is provided which supplies a third search run stop signal if the multipath signal exceeds a specific multipath setpoint value. The three search run stop signals are logically combined with one another by an AND gate and the result is made available as a static output signal and is provided as an input signal for a microprocessor.

Integrated circuit for detecting a received signal and circuit configuration

A charge pump has a reference stage that simulates the output stage of the paths, at least in terms of the output-side transistors of the paths. An equivalent symmetrical current is generated on a reference stage. The equivalent symmetrical current replicates the fault current and controls a device for regulating the second path.

Charge pump and PLL

A setting apparatus for setting the tuning voltage of a tunable resonant circuit has an amplification device which amplifies an oscillator tuning voltage, output by a phase locked loop, nonlinearly to produce the tuning voltage. The gain of the amplification device can be set by a digital gain control signal. The signal resolution of the setting apparatus can be controlled in different ways as a function of the gain by using two differently driven digital/analog converters.

Apparatus for setting the tuning voltage of tunable resonant circuits

A PLL synthesizer circuit is disclosed having a programmable divider circuit driven by a controller (microprocessor) for selecting a desired output frequency (f ) of the PLL synthesizer circuit. An operating mode selector circuit optionally drives a receive operating mode and at least one further operating mode (frequency change operating mode) of the PLL synthesizer circuit. The PLL synthesizer circuit has a smaller settling time constant in the frequency change operating mode. The change into the frequency change operating mode is initiated by a detection of the drive of the programmable divider by means of a changed (new) drive value. The change from the frequency change operating mode into the receive operating mode is caused whenever the phase difference, that is to say the output signal of the phase detector falls below a predetermined threshold value.

Growing community of inventors

München, Germany

Hans-Eberhard Kröbel

Growing community of inventors

München, Germany

Hans-Eberhard Kr&ouml;bel

Hans-Eberhard Kröbel