Siemens Aktiengesellschaft

Infineon Technologies Ag

Hans-Dieter Oberle

Kurt Hoffmann

Oskar Kowarik

Sebastian Sattler

Rainer Kraus

Christian Robert Mueller

Ralf Arnold

Bernhard Lustig

Manfred Paul

Martin Glas

Peter Muhmenthaler

An electric tolerance analysis circuit for digital and digitized measured values has inputs for receiving a measured value, a reference value, and a tolerance value and also an output for transmitting an output value. The electric tolerance analysis circuit also has a checking device for checking the measured value using at least one prescribable tolerance criterion and has an output device for outputting an output value which is obtained from the state of the checking device, depending on whether or not the measured value meets the respective prescribed tolerance criterion.

Apparatus and method for tolerance analysis for digital and/or digitized measure values

An integrated circuit includes at least one input and output circuit including: a signal terminal that provides an external contact; a protective circuit coupled to the signal terminal; an input driver and/or an output driver coupled to the signal terminal via the protective circuit; and an additional circuit including a first input coupled to the signal terminal via the protective circuit, and an output that provides a test value for operation of the input and output circuit.

Input and output circuit of an integrated circuit and a method for testing the same

To determine the period length of a first signal, the length is measured by counting the periods of a second signal with a shorter period length. To measure the fluctuations of the period length of the first signal whilst also taking into account the fluctuations of the period length of the second signal, the measurement is carried out for two different values of the period length of the second signal. Both the fluctuations of the period length of the first signal and the accumulated fluctuations of the period length of the second signal are calculated independently of one another from the two values. The method enables the period length fluctuations of a first signal that originates from a phase-locked loop to be detected.

Method and device for detecting period length fluctuations of periodic signals

In order to test the input and output drivers of a circuit, in particular an integrated semiconductor circuit, a method and apparatus is provided to connect the input or output drivers assigned to individual signal connections of the circuit to be tested in series to a ring oscillator or to an open chain with the oscillation of the ring oscillator or the delay time being evaluated. By providing appropriate controllable switches, the configuration of the ring oscillator or the chain can be altered variably depending on the input or output drivers to be tested respectively. In this way an 'at-speed' and 'leakage' test of all input and output drivers, including the external signal connections, are possible with all of these having to be connected to a rapid test unit.

Method and apparatus for the testing of input/output drivers of a circuit

A semiconductor memory is subdivided into a plurality of function units and has m leads addressable from outside, internal signal lines leading from the function units to the leads, internal signal lines connecting the function units with one another, and a test unit recognizing a test mode from a code word applied to k leads, where k.ltoreq.m. A device switches over from a memory mode to the test mode. The test unit decouples at least one of the signal lines leading to the leads from an associated lead of the semiconductor memory and connects the lead to an internal signal line connecting the function units.

Integrated semiconductor memory device capable of switching from a

A circuit configuration and method for testing storage cells of an integrated semiconductor memory precharges a pair of external bit lines to mutually complementary logic levels. All of the storage cells of a word line are always read-out in parallel. In a 'no fault' situation the pair of external bit lines retains its precharge level, whereas in the case of a fault, the level of the external bit line which is precharged to logical 1 falls. This is recognized by a discriminator circuit and analyzed.

Circuit configuration and a method of testing storage cells

A redundancy decoder of an integrated semiconductor memory having a plurality of decoder stages containing a switching transistor and a separable connection having respective conditions in which the separable connection is severed and intact, as well as at least one charging transistor, comprising, in each of the decoder stages, an addressing circuit connected to and between the switching transistor and the separable connection of the respective decoder stages, the addressing circuit being electrically simulatable when the respective separable connection is in the intact condition thereof.

Testable redundancy decoder of an integrated semiconductor memory

A method and circuit configuration for the parallel input of data items in the form of a test pattern into a block of a semiconductor memory having a plurality of storage cells. For test purposes, data items are simultaneously input in parallel into the storage cells.

Growing community of inventors

Puchheim, Germany

Hans-Dieter Oberle