Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Hans Boehm

Dhruva Ranjan Chakrabarti

Robert S Schreiber

Pramod G Joisha

Prithviraj Banerjee

Pablo Faraboschi

Methods, apparatus, systems and articles of manufacture are disclosed to control a cache. An example method includes monitoring cache lines in a cache, the cache lines storing recently written data to the cache, the recently written data corresponding to main memory, comparing a total quantity of the cache lines to a threshold that is less than a cache line storage capacity of the cache, and causing a write back of at least one of the cache lines to the main memory when a store event causes the total quantity of the cache lines to satisfy the threshold.

Cache controller for non-volatile memory

A technique includes performing an update to a location of a non-volatile memory. The update is created by execution of at least one machine executable instruction of a plurality of machine executable instructions. The technique includes using a processor-based machine to selectively track the update to allow recovery of the execution to a given consistency point based at least in part on whether the machine executable instruction(s) creating the update are located within a synchronized section of the plurality of machine executable instructions.

Non-volatile memory update tracking

A parallel-code optimization system includes a Procedural Concurrency Graph (PCG) generator. The PCG generator produces an initial PCG of a computer program including parallel code, and determines a refined PCG from the initial PCG by applying concurrency-type refinements and interference-type refinements to the initial PCG. The initial PCG and the refined PCG include nodes and edges connecting pairs of the nodes. The nodes represent defined procedures in the parallel code, and each edge represents a may-happen-in-parallel relation, and is associated with a set of lvalues that represents the immediate interference between the corresponding pair of nodes.

Procedural concurrency graph generator

A log entry is created in persistent memory that represents a modification to a variable that resides in persistent memory. A log entry is created in persistent memory that represents a synchronization operation. A program-order based dynamic ordering relationship is created between two successive log entries within an execution entity. A synchronization-order based dynamic ordering relationship is created between two log entries corresponding to synchronization operations in concurrently executing distinct execution entities of said execution instance.

Logging modifications to a variable in persistent memory

A parallel-code optimization system includes a siloed program reference-identifier and an intermediate representation (IR) updater. The siloed program reference identifier determines siloed program references in parallel code, wherein siloed program references are free of cross-thread interference. The IR updater modifies data-flow abstractions based on the identified siloed program references.

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Palo Alto, CA, United States of America

Hans Boehm