International Business Machines Corporation

Hanno Ulrich

Gary E Strait

Pak-kin Mak

Craig Raymond Walters

Timothy Carl Bronson

Vesselina K Papazova

Garrett M Drapala

Norbert Hagspiel

Kathryn Marie Jackson

Lisa Cranton Heller

Ute Gaertner

Deanna Postles Dunn Berger

Rebecca S Wisniewski

Joshua D Massover

Matthias Klein

Robert J Sonnelitter, Iii

Ulrich Mayer

Mark Anthony Check

David S Hutton

Diana Lynn Orf

Keith N Langston

Hong Deng

Embodiments are directed to methodologies for efficiently sampling data for analysis by a pipeline analysis algorithm. The amount of sampled data is maximized without increasing sampling overhead by sampling 'non-pipeline activity' data if the subject pipeline is inactive during the sampling time. The non-pipeline activity data is selected to include overall system information that is relevant to the subject pipeline's performance but is not necessarily dependent on whether the subject pipeline is active. In some embodiments, the non-pipeline activity data allows for confirmation of a pipeline performance characteristic that must otherwise be inferred by the subsequent pipeline analysis algorithm from data sampled while the pipeline was active. In some embodiments, the non-pipeline activity data allows the pipeline analysis algorithm to analyze additional performance characteristics that cannot otherwise be inferred from the data sampled while the pipeline was active.

Dual/multi-mode processor pipelines sampling

A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line. The determining being independent of transmission of information relating to the cache line from one or more other nodes of the one or more other regions of nodes.

Granting exclusive cache access using locality cache coherency state

Embodiments are directed to systems and methodologies for efficiently sampling data for analysis by a pipeline analysis algorithm. The amount of sampled data is maximized without increasing sampling overhead by sampling 'non-pipeline activity' data if the subject pipeline is inactive during the sampling time. The non-pipeline activity data is selected to include overall system information that is relevant to the subject pipeline's performance but is not necessarily dependent on whether the subject pipeline is active. In some embodiments, the non-pipeline activity data allows for confirmation of a pipeline performance characteristic that must otherwise be inferred by the subsequent pipeline analysis algorithm from data sampled while the pipeline was active. In some embodiments, the non-pipeline activity data allows the pipeline analysis algorithm to analyze additional performance characteristics that cannot otherwise be inferred from the data sampled while the pipeline was active.

Dual/multi-mode processor pipeline sampling

An aspect includes a method for operating on translation look-aside buffers (TLBs) in a multiprocessor environment including a plurality of logical partitions as zones. The method includes concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones including the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones including the second zone. The second set of zones consists of separate zones from the first set of zones. Based on receiving the first quiesce request, only processors of the first set of zones are quiesced. Based on the processors of the first set of zones being quiesced, a first operation is performed on the TLBs. Based on the first operation being performed, the processors of the first set of zones are un-quiesced.

Operating on translation look-aside buffers in a multiprocessor environment

A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.

Memory ordered store system in a multiprocessor computer system

A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time.

Providing multiple quiesce state machines in a computing environment

The exemplary embodiment of the present invention relates to a generalized LRU algorithm is provided that is associated with a specified cache associativity line set value that is determined by a system user. As configured, the LRU algorithm as presented can comprise n-levels for an LRU tree, each specified tree being individually analyzed within the LRU algorithm. Within each LRU tree level comprises the associativity line value can be further broken down into sub-analysis groups of any desired configuration, however, the total sub-analysis group configuration must equal the specified cache associativity line value.

Method, system and computer program product for generalized LRU in cache and memory performance analysis and modeling

The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise storage buffers that have the capability to efficiently support 128 byte or 256 byte I/O data transmission lines. The presently implemented storage buffer management scheme enables for a limited number of store buffers to be associated with a fixed number of storage state machines (i.e., queue positions) and thereafter the allowing for the matched pairs to be allocated in order to achieve maximum store throughput for varying combinations of store sizes of 128 and 256 bytes.

Method, system and computer program product for enhanced shared store buffer management scheme with limited resources for optimized performance

Feedback control algorithms for controlling a given simulation model which relates to a computer-program-based method and respective system for providing a feedback control for a given set of control quantities of a simulation model, comprising a plurality of iterated simulation runs each of which consumes a considerable amount of time. Each single run is performed with a setting of starting values for certain entry control quantities suited to control certain target quantities. The respective next setting of entry quantities is based on the value of the target quantities measured in the preceding simulation run. In order to provide for a fast convergence of the target quantities to a final, predetermined value, the following formula is applied: where&#x3bd;=()u is the final value of the target control quantity aimed at u, its value achieved up to iteration n of the simulation run and &#x3c1;is a suitable system parameter. &#x3c7; is a certain entry quantity suited to make uconverge against u, and &#x3c7;'is the value of &#x3c7; to be chosen for the next iteration.

Feedback process to model CP utilization in multi-processor performance models

The invention relates to a method and respective system for accessing a cache memory in a computer system, wherein the cache memory is split up in at least two segments, wherein the cache memory is accessed by a plurality of competing cache memory requests via a number of commonly used input registers, wherein a cache segment model is utilized for reflecting the cache use by said competing requests, wherein cache memory requests are processed by a processing pipe and wherein each cache-request, before entering the processing pipe, is checked whether the segments of the cache memory are available at the cycle it needs, wherein said memory comprises the steps of:

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Tuebingen, Germany

Hanno Ulrich