Siemens Aktiengesellschaft

Hanno Melzner

Armin Kohlhase

Stephan Auer

Hermann Wendt

Dominique Savignac

Dietrich Widmann

Wolfgang Hoenlein

Manfred Menke

Wolfgang Muller

Helmut Joswig

A memory device includes a multiplicity of memory cells disposed on a substrate for at least intermittent stable storage of at least two different information states. A writing device is associated with the memory cells for selectively putting one of the multiplicity of memory cells into a predetermined information state by external action. A reading device is associated with the memory cells for external detection of a current or chronologically preceding information state of a selected memory cell. The memory cells have a miniaturized mechanical element. The production of such a memory device is performed with the following steps: full-surface application of a first insulator layer onto a main surface of a substrate; full-surface application of a diaphragm layer being formed of an electrically conductive material onto the first insulator layer; structuring of the diaphragm layer in such a way that first conductor tracks are formed, which have enlargements at points of the memory cells; isotropic etching of the first insulator layer, using the structured diaphragm layer as an etching mask, until such time as a sharp point remains behind in the middle, immediately beneath the enlargement; and removal of all of the material of the fist insulator layer on the underside of the enlargement, thus forming a diaphragm.

Method for producing a memory device

A capacitor in a semiconductor configuration, especially a DRAM, includes an electrode structure having a plurality of spaced-apart elements being electrically connected with a connecting structure and all including p-conductive material with a doping &gt;10.sup.10 cm.sup.-3. The elements of the electrode structure are either stacked or disposed side by side and may be cup-shaped. In a production process, a layer sequence of alternatingly one p.sup.- -doped and one p.sup.+ -doped layer is produced, which receives an opening through the use of anisotropic etching. At least in a peripheral region of the opening, a p.sup.+ -zone is created, which connects the layer sequence and forms the connecting structure. Next, the p.sup.- -doped layers are etched selectively to the p.sup.+ -doped layers, a capacitor dielectric is deposited, and a counterelectrode is produced.

Capacitor in a semiconductor configuration and process for its production

An apparatus for the chemical-mechanical polishing of wafers has a rotating disk provided with a polishing body, a supply device for a polishing fluid and a holding device for the wafer. An axis of the disk runs parallel to the surface of the wafer. A cylindrical edge surface of the disk is provided with the polishing body in such a way that a trench with a specific cross section can be made in the wafer.

Apparatus for the chemical-mechanical polishing of wafers

A semiconductor array with self-adjusted contacts includes a substrate having a surface, at least two mutually spaced-apart doped regions extending in a first lateral direction on the surface, and insulated regions each being associated with a respective one of the doped regions and extending in the first lateral direction on the same side. Contact surfaces each extend in the first lateral direction above a respective one of the doped regions and at least partially above the insulated region associated with the one doped region. An insulating layer has contact holes each being formed therein above a respective one of the contact surfaces for receiving a self-adjusted contact. A method for producing a semiconductor array with self-adjusted contacts includes producing one of the contact surfaces with a first fragment being a part of the contact surface extending above the doped region and a second fragment being a part of the contact surface extending above the insulated region. The first fragment is produced with a non-photolithographic process avoiding edge location errors. The second fragment extends above the first fragment and therefore above the doped region by at least a length of a maximum edge location error, as long as no edge location errors occur.

Semiconductor array with self-adjusted contacts

Memory device and production method

A method for producing a contact hole to a first doped region of a first conductivity type in a semiconductor wafer having doped regions of the first and of a second conductivity type, includes producing a first doped region in a substrate having a surface, and bounding the first doped region with insulation regions at least at the surface of the substrate. A diffusion barrier layer is produced leaving at least the first doped region free and covering a second doped region of a second conductivity type. An undoped silicon layer is deposited over the entire surface. A doped region is selectively produced in the silicon layer by implantation, and the doped region overlaps a region for a contact hole. Undoped portions of the silicon layer are selectively removed relative to the doped region. An insulation layer is produced over the entire surface. A contact hole is opened in the insulation layer by selective anisotropic etching relative to the doped region of the silicon layer.

Method for producing a contact hole to a doped region

A semiconductor memory configuration and a manufacturing process for the semiconductor memory configuration use a polishing process in the manufacture of a semiconductor memory configuration with stacked-capacitor-above-bit-line memory cells. At least TC pillars are created with the aid of a CMP step and a completely planarized surface existing prior to the manufacture of the bit line. Further CMP steps are advantageously used, inter alia, in the manufacture of a TB pillar of a bit line which is countersunk in a trench and of a lower capacitor plate, as well as to completely planarize a cell array and a periphery prior to interconnection of the circuit.

Semiconductor memory device having a transistor, a bit line, a word line

Integrated semiconductor circuit or micromechanical component and

An improved method for manufacturing a bit line via hole for a memory cell is disclosed wherein changes in the topography of a conductive layer forming the cell plate that are caused by the capacitor are utilized for producing an etching mask for the bit line via hole. A depression is formed because the second source/drain region of the transistor which is to be contacted by the bit line is not covered by the lower capacitor plate. The etching mask is not produced in the depression but only at the raised locations and is therefore self-aligned above the second S/D region.

Method for manufacturing a bit line via hole in a memory cell

A self-aligned through hole (5), particularly a bit line through hole to a source/drain region (2) that is self-aligned relative to the word line, is produced in neighboring word lines (3a) having a greater spacing from one another in the proximity of the source/drain region than at other locations. Narrow spacings are completely filled by surface-wide deposition of an insulating intermediate layer and subsequent, anisotropic etching, whereas insulating spacers (4') are formed in enlarged interspaces at side walls of the encapsulated word lines (3) and thereby form a self-aligned through hole.

Manufacturing method for a self-aligned through hole and semiconductor

Compact semiconductor storage arrangement and method for its production

The arrangement relates to bit lines which are widened to form contact surfaces (11, 21, 31, 41, 51) at the contacts (10, 20, 30, 40, 50) to underlying cells, the contacts being arranged in an at least a three-fold stagger. A minimum space requirement is achieved in conjunction with increased reliability when the distance b.sub.Sp between edges of adjacent bit lines has the same value everywhere, and the contact surfaces can thereby be enlarged.

Bit line arrangement for integrated circuits

A conductor track configuration for very large-scale integrated circuits includes at least two lower conductor tracks extending substantially in a first direction and at least two upper conductor tracks extending substantially in the first direction above the lower conductor tracks. Each of the lower conductor tracks is subdivided into segments, defining gaps between the segments. Each respective one of the segments has one contact leading to the upper conductor track disposed above the one segment. The lower conductor tracks adjacent the segments, as seen in a second direction, have one of the gaps at least in the vicinity of one of the contacts.

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Unterhaching, Germany

Hanno Melzner