Infineon Technologies Ag

Hanno Melzner

Thoralf Kautzsch

Dirk Meinhold

Henning Feick

Dirk Offenberg

Stefano Parascandola

Ines Uhlig

Thomas Bever

Olivier Rizzo

Jacques Herry

Hans-Joachim Schulze

Peter Irsigler

Sebastian Schmidt

Anton Mauder

Oliver Hellmund

Stefan Miethaner

Brigitte Wirtz

Peter Morguet

Bernhard Fehr

Markus Dankerl

Ottmar Koeder

Angela Engels

Karl Heinz Hitzlberger

A transistor device may include a semiconductor body, a plurality of cell regions each comprising a plurality of transistor cells that are at least partially integrated in the semiconductor body and that each comprise a respective gate electrode, a plurality of routing channels each arranged between two or more of the cell regions, a gate pad arranged above a first surface of the semiconductor body, and a plurality of gate runners each coupled to the gate pad and each arranged in one of the plurality of routing channels. Each of the plurality of gate runners may be associated with one of the plurality of cell regions such that the gate electrodes in each of the plurality of cell regions are connected to an associated gate runner, and each of the plurality of routing channels comprises two or more gate runners that are routed in parallel and spaced apart.

Transistor device

A molding compound and a semiconductor arrangement with a molding compound are disclosed. The molding compound includes a matrix and a filler including filler particles. The filler particles each include a core with an electrically conducting or a semiconducting material and an electrically insulating cover.

Molding compound and semiconductor package with a molding compound

Embodiments related to controlling of photo-generated charge carriers are described and depicted. At least one embodiment provides a semiconductor substrate comprising a photo-conversion region to convert light into photo-generated charge carriers; a region to accumulate the photo-generated charge carriers; a control electrode structure including a plurality of control electrodes to generate a potential distribution such that the photo-generated carriers are guided towards the region to accumulate the photo-generated charge carriers based on signals applied to the control electrode structure; a non-uniform doping profile in the semiconductor substrate to generate an electric field with vertical field vector components in at least a part of the photo-conversion region.

Controlling of photo-generated charge carriers

A membrane structure is provided. The membrane structure may include: a membrane; at least one hole extending into the membrane configured to receive a fluid. The membrane may include a plurality of electrodes arranged to provide one or more electric fields to control a movement of the fluid within the at least one hole.

Ion pump

In accordance with an embodiment of the present invention, a semiconductor device includes a first metal line in a first insulating layer, and a via having a portion surrounding a portion of a first sidewall of the first metal line.

Vias and methods of formation thereof

In accordance with an embodiment of the present invention, a semiconductor device includes a first metal line disposed in a first insulating layer, and a via having a portion surrounding a portion of a first sidewall of the first metal line.

A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid in a first portion of a layout causing a problematic spot on the substrate.

Method and apparatus for providing a layout defining a structure to be patterned onto a substrate

A method for simplifying metal shapes in an integrated circuit including receiving an incoming wire layout for at least one metal layer of an integrated circuit, the incoming wire layout for the at least one layer including a plurality of wires running in a preferred direction and a plurality of vias connected thereto. The method further includes segmenting each of the wires into a plurality of bricks according to a set of equally spaced parallel grid lines extending in direction which is perpendicular to the preferred direction such that each wire comprises a series of consecutive bricks with brick boundaries between consecutive bricks occurring at a grid line, defining each brick as a regular or complex brick based on at least one brick criteria, and defining brick groups based on one or more grouping criteria, wherein each group contains one or more consecutive bricks of a same wire and each brick belongs to only one group so that each wire comprises a series of one or more consecutive groups, and wherein groups containing at least one complex brick are defined as complex groups.

Method of making in an integrated circuit including simplifying metal shapes

A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes defining intracell wiring in at least one layer positioned above a substrate, the intracell wiring connecting to structures below the at least one layer and forming one or more terminals, and defining one or more candidate wires for at least one terminal to use as pre-defined intercell wiring for connection to the at least one terminal. The method further includes arranging selected cells from the cell library to form a desired layout of an integrated circuit, and routing intercell wiring so as to interconnect the selected cells to achieve a desired function of the integrated circuit including using only selected candidate wires for intercell wiring within borders of each of the selected cells.

Method of making an integrated circuit using pre-defined interconnect wiring

Method of making an integrated circuit including simplifying metal shapes

A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes routing a intracell wiring in at least one layer positioned above a substrate, with the conductors being spaced apart from one another so as to have gaps there between, and configuring and positioning a plurality of fill structures in the gaps. The method further includes arranging selected logic cells from the cell library to form a desired layout of the integrated circuit, routing interconnect wiring between the selected logic cells in the at least one layer, and removing fill structures at positions that conflict with the routing of the interconnect wiring.

Method of making an integrated circuit having fill structures

A method is provided for optimizing routing on a substrate such as an integrated circuit or printed circuit board. The method defines a plurality of parallel strips on an initial routing layout of conductors for a layer of an integrated circuit. Each conductor within each strip defines a brick. For each of the plurality of strips, a spacing between bricks and a brick thickness of each brick is adjusted as a function of i) a location of a brick in adjacent strips corresponding to the same conductor; ii) a desired brick thickness; and iii) a desired brick spacing.

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Sauerlach, Germany

Hanno Melzner